公开(公告)号：WO2010132283A1

公开(公告)日：2010-11-18

申请号：PCT/US2010/033967

申请日：2010-05-07

Applicant: GLOBALFOUNDRIES INC. ,  WEI, Andy ,  WAITE, Andrew

Inventor： WEI, Andy ,  WAITE, Andrew

IPC: H01L21/8238 ,  H01L27/06 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/0629 ,  H01L28/20

Abstract: In a semiconductor device comprising sophisticated high-k metal gate structures formed in accordance with a replacement gate approach, semiconductor-based resistors may be formed above isolation structures (103D) substantially without being influenced by the replacement gate approach. Consequently, enhanced area efficiency may be achieved compared to conventional strategies, in which the resistive structures may have to be provided on the basis of a gate electrode metal, while, nevertheless, a low parasitic capacitance may be accomplished due to providing the resistive structures above the isolation structure.

Abstract translation: 在包括根据替换栅极方法形成的复杂高k金属栅极结构的半导体器件中，基本上不受更换栅极方法的影响，可以在隔离结构（103D）之上形成基于半导体的电阻器。 因此，与常规策略相比，可以实现增强的面积效率，其中电阻结构可能必须基于栅电极金属提供，而尽管如此，可以通过提供上述电阻结构来实现低寄生电容 隔离结构。

公开(公告)号：WO2010132130A1

公开(公告)日：2010-11-18

申请号：PCT/US2010/023169

申请日：2010-02-04

Applicant: GLOBALFOUNDRIES Inc. ,  FRANK, Michael

Inventor： FRANK, Michael

IPC: H04L9/06

CPC classification number: H04L9/0631 ,  H04L2209/125

Abstract: Encrypting information involving the execution of a first instruction and a second instruction on a processor. The first instruction causes the processor to perform an AddRoundKey transformation followed by a ShiftRows transformation. The second instruction causes the processor to perform a ShiftRows transformation followed by a MixColumns transformation. These instructions are useful for performing AES encryption. The first and second instructions also have inverse modes that may be used to perform AES decryption.

Abstract translation: 在处理器上加密涉及执行第一指令和第二指令的信息。 第一条指令使处理器执行AddRoundKey变换，随后进行ShiftRows转换。 第二条指令使处理器执行ShiftRows转换，然后执行MixColumns转换。 这些指令对于执行AES加密很有用。 第一和第二指令也具有可用于执行AES解密的逆模式。

公开(公告)号：WO2010096296A1

公开(公告)日：2010-08-26

申请号：PCT/US2010/023489

申请日：2010-02-08

Applicant: GLOBALFOUNDRIES INC. ,  HARGROVE, Michael ,  YANG, Frank, Bin ,  PAL, Rohit

Inventor： HARGROVE, Michael ,  YANG, Frank, Bin ,  PAL, Rohit

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/51

CPC classification number: H01L21/28088 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Methods are provided for forming a semiconductor device (10, 100) comprising a semiconductor substrate (14, 110). In one embodiment, the method includes the steps of: forming a high-k dielectric layer (24, 140) overlying the semiconductor substrate; forming a metal-comprising gate layer (48, 166) overlying the high-k dielectric layer; forming a doped silicon-comprising capping layer (52, 170) overlying the metal-comprising gate layer; and depositing a silicon-comprising gate layer (60, 178) overlying the doped silicon-comprising capping layer.

Abstract translation: 提供了用于形成包括半导体衬底（14,110）的半导体器件（10,100）的方法。 在一个实施例中，该方法包括以下步骤：形成覆盖半导体衬底的高k电介质层（24,140）; 形成覆盖所述高k电介质层的包含金属的栅极层（48,166）; 形成覆盖所述含金属栅极层的掺杂的含硅覆盖层（52,170）; 以及沉积覆盖所述掺杂的含硅覆盖层的含硅栅极层（60,178）。

公开(公告)号：WO2010062334A1

公开(公告)日：2010-06-03

申请号：PCT/US2009/005838

申请日：2009-10-28

Applicant: GLOBALFOUNDRIES INC. ,  RYAN, E., Todd ,  SCHUEHRER, Holger ,  RHEE, Seung-Hyun

Inventor： RYAN, E., Todd ,  SCHUEHRER, Holger ,  RHEE, Seung-Hyun

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A semiconductor package is provided having reduced tensile stress. The semiconductor package includes a package substrate and a semiconductor die. The semiconductor die is coupled electrically and physically to the package substrate and includes a stress relieving layer incorporated therein. The stress relieving layer has a predetermined structure and a predetermined location within the semiconductor die for reducing tensile stress of the semiconductor package during heating and cooling of the semiconductor package.

Abstract translation: 提供具有降低的拉伸应力的半导体封装。 半导体封装包括封装衬底和半导体管芯。 半导体管芯电耦合和物理耦合到封装衬底并且包括并入其中的应力消除层。 应力消除层在半导体管芯内具有预定的结构和预定位置，用于在半导体封装的加热和冷却期间减小半导体封装的拉伸应力。

公开(公告)号：WO2010021683A1

公开(公告)日：2010-02-25

申请号：PCT/US2009/004690

申请日：2009-08-17

Applicant: GLOBALFOUNDRIES INC. ,  DAKSHINA-MURTHY, Srikanteswara ,  GERHARDT, Martin

Inventor： DAKSHINA-MURTHY, Srikanteswara ,  GERHARDT, Martin

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/265 ,  H01L29/10

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66636

Abstract: Methods are provided for fabricating a MOS transistor having self-aligned stressor and extension regions. A method comprises forming a gate stack overlying a layer of semiconductor material and forming a spacer about sidewalls of the gate stack. The method further comprises forming cavities in the layer of semiconductor material, wherein the cavities are substantially aligned with the spacer. The method further comprises forming a stress-inducing semiconductor material in the cavities, and implanting ions of a conductivity- determining impurity type into the stress-inducing semiconductor material using the gate stack and the spacer as an implantation mask.

Abstract translation: 提供了用于制造具有自对准应力源和延伸区域的MOS晶体管的方法。 一种方法包括形成覆盖在半导体材料层上的栅极堆叠并且围绕栅堆叠的侧壁形成间隔物。 该方法还包括在半导体材料层中形成空腔，其中空腔基本上与间隔物对准。 该方法还包括在空腔中形成应力诱导半导体材料，并且使用栅极堆叠和间隔物作为注入掩模将导电性确定杂质类型的离子注入到应力诱导半导体材料中。

公开(公告)号：WO2009148533A1

公开(公告)日：2009-12-10

申请号：PCT/US2009/003246

申请日：2009-05-28

Applicant: GLOBALFOUNDRIES INC. ,  CHO, Hyun-Jin

Inventor： CHO, Hyun-Jin

IPC: H01L27/102 ,  G11C11/39 ,  H01L21/332 ,  H01L29/74 ,  H01L27/06

CPC classification number: H01L27/1027 ,  G11C11/39 ,  H01L27/0817

Abstract: A method for fabricating a gated lateral thyristor-based memory device (gltram) is provided. A semiconductor layer (406) is provided that includes first, second, third and fourth well regions (463, 471, 486, 493) of a first conductivity type in the semiconductor layer 406. A first gate structure (465/408) overlies the first well region (463), a second gate structure (475/408) overlies the second well region (471), a third gate structure (485/408) overlies the third well region (486) and is integral with the second gate structure (475/408), and a fourth gate structure (495/408) overlies the fourth well region (493). Sidewall spacers (467) are formed adjacent a first sidewall (414) of the first gate structure (465/408) and sidewalls (412, 413, 416, 417, 418, 419) of the second through fourth gate structures (475/408, 485/408, 495/408). In addition, an insulating spacer block (469) is formed overlying a portion (468) of the first well region (463) and a portion of the first gate structure (465/408). The insulating spacer block (.469) is adjacent a second sidewall (415) of the first gate structure (465/408). A first source region (472) is formed adjacent the first gate structure (465/408), a common drain/cathode region (474/464) is formed between the first and second gate structures (465/408, 475/408), a second source region (482) is formed adjacent the third gate structure (485/408), a common drain/source region (484/492) is formed between the third and fourth gate structures (485/408, 495/408), and a drain region (494) is formed adjacent the fourth gate structure (495/408). A first base region (468) is formed that extends into the first well region (463) under the insulating spacer block (467) adjacent the first gate structure (465/408), and an anode region (466) is formed in the first well region (463) that extends into the first well region (463) adjacent the first base region (468).

Abstract translation: 提供了一种用于制造门控侧栅晶闸管的存储器件（gltram）的方法。 提供半导体层（406），其包括半导体层406中的第一导电类型的第一，第二，第三和第四阱区域（463,471,468,493）。第一栅极结构（465/408）覆盖 第一阱区域（463），第二栅极结构（475/408）覆盖第二阱区域（471），第三栅极结构（485/408）覆盖第三阱区域（486）并与第二栅极结构 （475/408）和第四栅极结构（495/408）覆盖在第四阱区（493）上。 侧壁间隔件（467）与第一栅极结构（465/408）的第一侧壁（414）和第二至第四栅极结构（475/408）的侧壁（412,413,416,417,418,419）相邻地形成 ，485 / 408,495 / 408）。 此外，绝缘间隔块（469）形成为覆盖第一阱区（463）的一部分（468）和第一栅结构（465/408）的一部分。 绝缘间隔块（.469）与第一栅极结构（465/408）的第二侧壁（415）相邻。 在第一栅极结构（465/408）附近形成第一源极区（472），在第一和第二栅极结构（465/408,475 / 408）之间形成共同的漏极/阴极区（474/464） 在第三栅极结构（485/408）附近形成第二源极区（482），在第三和第四栅极结构（485/408,495/408）之间形成公共漏极/源极区（484/492） 并且与第四栅极结构（495/408）相邻形成漏区（494）。 形成在第一栅极结构（465/408）附近延伸到绝缘间隔块（467）下面的第一阱区域（463）中的第一基极区域（468），并且阳极区域（466）形成在第一基极区域 （463）延伸到邻近第一基区（468）的第一阱区（463）中。

公开(公告)号：EP3185282B1

公开(公告)日：2018-08-29

申请号：EP17155850.5

申请日：2014-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Miner, Stephen Bradley ,  Fosnight, William John ,  Gallagher, Ryan

IPC: H01L21/67 ,  H01L21/68 ,  B25J19/02

CPC classification number: H01L21/67265 ,  G05B19/4184 ,  G05B19/41875 ,  G05B2219/37224 ,  G05B2219/45031 ,  H01L21/67259 ,  H01L21/67389 ,  H01L21/68 ,  H01L21/68707 ,  Y02P90/04 ,  Y10S901/02 ,  Y10S901/27

Abstract: Systems, machines, and methods for monitoring wafer handling are disclosed herein. A system for monitoring wafer handling includes a sensor and a controller. The sensor is capable of being secured to an assembled wafer handling machine. The controller is in electronic communication with the sensor and includes control logic. The control logic is configured to store a reference output of the sensor when the wafer handling machine is aligned and is configured to generate an indication signal when a difference between the reference output and a current output of the sensor exceeds a threshold.

公开(公告)号：EP2595182A1

公开(公告)日：2013-05-22

申请号：EP11189233.7

申请日：2011-11-15

Applicant: IMEC ,  GlobalFoundries, Inc.

Inventor： Baklanov, Mikhaïl ,  Iacopi, Francesca ,  Vanhaelemeersch, Serge

IPC: H01L21/768

CPC classification number: H01B19/04 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826

Abstract: The invention relates to a method for treating a surface of a porous material in an environment, said method comprising the steps of:
I. Setting the temperature of said surface to a value T1 and setting the pressure of said environment to a value P1,
II. contacting said surface with a fluid having a solidifying temperature at said pressure value P1 above said value T1 and having a vaporizing temperature at said pressure value P1 below 80°C, thereby solidifying said fluid in pores of said material, thereby sealing said pores,
III. treating said surface, wherein said treatment is preferably an etching or a modification of said surface,
IV. Setting the temperature of said surface to a value T2 and setting the pressure of said environment to a value P2 in such a way as to vaporize said fluid,

Abstract translation: 本发明涉及一种在环境中处理多孔材料的表面的方法，所述方法包括以下步骤：I.将所述表面的温度设定为T1，将所述环境的压力设定为值P1，II 。 使所述表面与具有高于所述值T1的所述压力值P1的凝固温度的流体接触并且具有在所述压力值P1低于80℃的蒸发温度，从而使所述流体在所述材料的孔中固化，从而密封所述孔，III 。 处理所述表面，其中所述处理优选是所述表面的蚀刻或修饰。 将所述表面的温度设定为值T2，并将所述环境的压力设定为值P2，以使所述流体蒸发，

公开(公告)号：EP2176740B1

公开(公告)日：2011-03-02

申请号：EP08780088.4

申请日：2008-07-10

Applicant: GlobalFoundries, Inc.

Inventor： SHEN, Gene, W. ,  LIE, Sean

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3822 ,  G06F9/30152 ,  G06F9/3814 ,  G06F9/382

Abstract: A mechanism for superscalar decode of variable length instructions. A length decode unit may obtain a plurality of instruction bytes based on a scan window of a predetermined size. The instruction bytes may be associated with a plurality of variable length instructions, which are scheduled to be executed by a processing unit. The length decode unit may, for each instruction byte, estimate the start of a next variable length instruction following a current variable length instruction, and store a first pointer. A pre- pick unit may, for each instruction byte, use the first pointer to estimate the start of a subsequent variable length instruction following the next variable length instruction within the scan window, and store a second pointer. A pick unit may use a start pointer and related first and second pointers to determine the actual start of the variable length instructions within the scan window, and generate instruction pointers.

公开(公告)号：EP1005672B1

公开(公告)日：2010-10-06

申请号：EP96925347.5

申请日：1996-07-16

Applicant: GlobalFoundries, Inc.

Inventor： RAMAGOPAL, H., S. ,  HATTANGADI, Rajiv, M. ,  CHINNAKONDA, Muralidharan, S.

IPC: G06F9/38

CPC classification number: G06F9/3824 ,  G06F9/3834 ,  G06F9/3842