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    Semiconductor integrated circuit, method and program for designing the semiconductor integrated circuit
    41.
    发明申请
    Semiconductor integrated circuit, method and program for designing the semiconductor integrated circuit 有权
    半导体集成电路，设计半导体集成电路的方法和程序

    公开(公告)号：US20040075470A1

    公开(公告)日：2004-04-22

    申请号：US10671474

    申请日：2003-09-29

    Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

    Inventor： Nobuhiro Oodaira ,  Hiroyuki Mizuno ,  Yusuke Kanno ,  Koichiro Ishibashi ,  Masanao Yamaoka

    IPC: H03K019/094

    CPC classification number: G06F17/505 ,  H01L27/1203

    Abstract: A semiconductor integrated circuit that is well-balanced between increased operating speed and de creased power consumption caused by a leakage current. The gate cells of the circuit comprised of low threshold voltage MOSs are used for logic gates provided with three or more inputs, and gate cells comprised of high threshold voltage MOSs are generally used for logic gates provided with one or two inputs, sometimes on a case-by-case basis.

    Abstract translation: 一种半导体集成电路，其在增加的操作速度和由漏电流引起的降低的功耗之间平衡。 由低阈值电压MOS构成的电路的栅极单元用于设置有三个或更多个输入的逻辑门，并且由高阈值电压MOS构成的门单元通常用于设置有一个或两个输入的逻辑门，有时在一个情况下 逐案。

    IC card and method of manufacturing the same
    42.
    发明申请
    IC card and method of manufacturing the same 有权
    IC卡及其制造方法

    公开(公告)号：US20040062112A1

    公开(公告)日：2004-04-01

    申请号：US10668187

    申请日：2003-09-24

    Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

    Inventor： Hirotaka Nishizawa ,  Kenji Osawa ,  Akira Higuchi ,  Junichiro Osako ,  Tamaki Wada

    IPC: G11C007/00

    CPC classification number: G06K19/07743 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/14 ,  Y10S439/945 ,  Y10S439/946 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: The productivity of an IC card is to be improved. In a memory card of the type in which a memory body having a wiring substrate and a semiconductor chip mounted on a main surface of the wiring substrate is held so as to be sandwiched in between a first case and a second case, a planar outline of the memory body is smaller than half of a planar outline of the memory card. The memory body is disposed so as to be positioned closer to a first end side as one short side of the memory card with respect to a midline between the first end side and a second end side as an opposite short side of the memory card positioned on the side opposite to the first end side. The other area than the memory body-disposed area in the first and the second case is used as another functional area.

    Abstract translation: 提高IC卡的生产率。 在其中具有布线基板的存储体和安装在布线基板的主表面上的半导体芯片被夹持在第一壳体和第二壳体之间的类型的存储卡中，平面轮廓 存储器体小于存储卡的平面轮廓的一半。 存储体被布置成相对于位于第一端侧和第二端侧之间的中线的位置，更靠近作为存储卡的一个短边的第一端侧，作为位于存储卡的相对的短边 与第一端侧相对的一侧。 将第一和第二种情况下的存储体配置区域以外的区域用作另一功能区域。

    Manufacturing method of semiconductor integrated circuit device
    44.
    发明申请
    Manufacturing method of semiconductor integrated circuit device 失效
    半导体集成电路器件的制造方法

    公开(公告)号：US20040038494A1

    公开(公告)日：2004-02-26

    申请号：US10642658

    申请日：2003-08-19

    Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

    Inventor： Hidenori Sato ,  Yoshiyuki Hayashi ,  Toshio Ando

    IPC: H01L021/76

    CPC classification number: H01L21/0217 ,  C23C16/345 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/3185 ,  H01L27/11 ,  H01L27/1104

    Abstract: Described is a manufacturing method of a semiconductor integrated circuit device by depositing a silicon nitride film to give a uniform thickness over the main surface of a semiconductor wafer having a high pattern density region and a low pattern density region. This is attained by, upon depositing a silicon nitride film over a substrate having a high gate-electrode-pattern density region and a low gate-electrode-pattern density region by using a single-wafer cold-wall thermal CVD reactor, setting a flow rate ratio of ammonia (NH3) to monosilane (SiH4) greater than that upon deposition of a silicon nitride film over a flat substrate.

    Abstract translation: 描述了通过在具有高图案密度区域和低图案密度区域的半导体晶片的主表面上沉积氮化硅膜以获得均匀厚度的半导体集成电路器件的制造方法。 这是通过使用单晶片冷壁热CVD反应器在具有高栅电极图案密度区域和低栅电极图案密度区域的衬底上沉积氮化硅膜来实现的， 氨（NH 3）与甲硅烷（SiH 4）的比率大于在平坦基底上沉积氮化硅膜时的速率比。

    Semiconductor memory device
    45.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20040027896A1

    公开(公告)日：2004-02-12

    申请号：US10637549

    申请日：2003-08-11

    Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co. , Ltd.

    Inventor： Hiroki Ueno ,  Takashi Akioka ,  Kinya Mitsumoto ,  Akihisa Aoyama ,  Masao Shinozaki

    IPC: G11C007/00

    CPC classification number: G11C5/063 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/419 ,  H01L27/11

    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

    Abstract translation: 为了减少在存储单元读出信号的位线和布置在其上方的信号传输线之间形成的寄生电容。 用于通过互补位线传送从存储单元MC读出的数据的第二互补全局位线布置在存储单元阵列的上方。 每个第二全局位线被布置成使得具有顶点为互补位线之一的部分的中心的三角形，另一个的另一个的部分的中心和第二全局位线的部分的直线布置在其上方 互补位线是一个等腰三角形。

    Semiconductor integrated circuit device
    46.
    发明申请
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US20040016977A1

    公开(公告)日：2004-01-29

    申请号：US10429771

    申请日：2003-05-06

    Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

    Inventor： Masayuki Miyazaki ,  Yusuke Kanno ,  Goichi Ono ,  Toshinobu Shinbo ,  Yoshihiko Yasu ,  Kazumasa Yanagisawa ,  Takashi Kuraishi

    IPC: H01L029/94

    CPC classification number: H03K19/01707 ,  H01L27/0928 ,  H03K19/0016 ,  H03K2217/0018

    Abstract: A body bias control system allows for independent design of a functional module, thereby reducing the burden of designing the module. The body bias control system provides a switch circuit having an area in which the body bias is controlled independently of its outside portion, for controlling the supply of body bias in the vicinity of the area. Preferably three types of switches are provided for switching the body bias to suitable levels for a standby mode, a mode of normal operation and a mode of high-speed operation.

    Abstract translation: 身体偏置控制系统允许功能模块的独立设计，从而减少设计模块的负担。 身体偏置控制系统提供了一种开关电路，该开关电路具有独立于其外部部分来控制身体偏压的区域，用于控制该区域附近的身体偏压的供应。 优选地，提供三种类型的开关用于将主体偏压切换到用于待机模式，正常操作模式和高速操作模式的适当水平。

    IC card
    48.
    发明申请
    IC card 审中-公开
    IC卡

    公开(公告)号：US20030230631A1

    公开(公告)日：2003-12-18

    申请号：US10449090

    申请日：2003-06-02

    Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

    Inventor： Hisataka Tsunoda ,  Keisuke Takata ,  Kazuki Watanabe ,  Norihisa Yamamoto ,  Kazuhiro Matsushita

    IPC: G06K019/06

    CPC classification number: G06K19/07769 ,  G06K19/0723 ,  G06K19/077 ,  G06K19/07749

    Abstract: In an IC card of dual-way type which is used in common as a non-contact/contact operation card, an isolation transistor is provided between a power supply voltage terminal and a contact power supply circuit. Non-contact/contact judging and switching unit 6 turns OFF, when it is detected that the IC card is operated in a non-contact operation mode, an isolation transistor to isolate between the power supply voltage terminal and contact power supply circuit. Accordingly, when the power supply voltage terminal is terminated with a ground terminal during the non-contact operation mode, erroneous operation of the IC card can surely be prevented. Since the power supply voltage terminal becomes equal to a reference potential in this case, monitoring of voltage of the power supply voltage terminal can be prevented and security of the IC card can also be improved remarkably.

    Abstract translation: 在作为非接触/接触操作卡共同使用的双向型IC卡中，隔离晶体管设置在电源电压端子和接触电源电路之间。 当检测到IC卡以非接触操作模式操作时，非接触/接触判断和切换单元6关闭，隔离晶体管隔离电源电压端子和接触电源电路。 因此，当在非接触操作模式期间电源电压端子用接地端子终止时，可以可靠地防止IC卡的错误操作。 由于电源电压端子在这种情况下变为等于基准电位，因此可以防止对电源电压端子的电压的监视，并且可以显着提高IC卡的安全性。

    Nonvolatile memory
    50.
    发明申请
    Nonvolatile memory 审中-公开
    非易失性存储器

    公开(公告)号：US20030110361A1

    公开(公告)日：2003-06-12

    申请号：US10270590

    申请日：2002-10-16

    Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

    Inventor： Akira Kanehira ,  Hiroyuki Uchida ,  Shinichi Kurogochi ,  Yoshikazu Iida

    IPC: G06F012/00

    CPC classification number: G06F11/1068

    Abstract: A nonvolatile memory is configured inclusive of a memory unit including a data area capable of writing data therein, and a management area capable of writing therein management information about the data written into the data area, and a memory control unit for controlling the operation of the memory unit. Under such a configuration, there is provided control means for instructing rewriting of next data with respect to a write error produced in the data area without instructing rewriting of the same data, and instructing rewriting of the same data with respect to a write error produced in the management area. Owing to its provision, an effective record rate can be avoided from falling below a rate for write data.

    Abstract translation: 非易失性存储器被配置为包括包括能够在其中写入数据的数据区的存储单元和能够写入关于写入数据区的数据的管理信息的管理区，以及存储器控制单元，用于控制 存储单元 在这种配置下，提供了控制装置，用于指示相对于在数据区中产生的写入错误重写下一个数据，而不指示重写相同的数据，并指示相对于产生的写入错误重写相同的数据 管理区域。 由于其规定，可以避免有效记录率低于写入数据的速率。

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