公开(公告)号：WO1995022085A1

公开(公告)日：1995-08-17

申请号：PCT/US1995001735

申请日：1995-02-09

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CHEN, Jang, Fung ,  MATTHEWS, James, A.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G03F07/20

CPC classification number: G03F1/36 ,  G03F7/70125 ,  G03F7/70433

Abstract: In a lithographical tool utilizing off-axis illumination, masks to provide increased depth of focus and minimize CD differences between certain features are disclosed. A first mask for reducing proximity effects between isolated and densely packed features and increasing depth of focus (DOF) of isolated features is disclosed. The first mask comprises additional lines (214) referred to as scattering bars, disposed next to isolated edges. The bars are spaced a distance from isolated edges such that isolated and densely packed edge gradients substantially match so that proximity effects become negligible. The width of the bars is set so that a maximum DOF range for the isolated feature is achieved. A second mask, that is effective with quadrupole illumination only, is also disclosed. This mask "boosts" intensity levels and consequently DOF ranges for smaller square contacts so that they approximate intensity levels and DOF ranges of larger elongated contacts. Increasing the intensity levels in smaller contacts reduces critical dimension differences between variably sized contact patterns when transferred to a resist layer. The second mask comprises additional openings, referred to as anti-scattering bars, disposed about the square contact openings. The amount of separation between the edge of the smaller contact and the anti-scattering bars determines the amount of increased intensity. The width of the anti-scattering bars determines the amount of increase in DOF range. Both scattering bar and anti-scattering bars are designed to have widths significantly less than the resolution of the exposure tool so that they do not produce a pattern during exposure of photoresist.

Abstract translation: 在利用离轴照明的光刻工具中，公开了提供增加的聚焦深度并最小化某些特征之间的CD差异的掩模。 公开了用于减少隔离和密集堆叠特征之间的邻近效应的第一掩模，并且增加了隔离特征的增加的焦深（DOF）。 第一掩模包括邻近隔离边缘设置的称为散射棒的附加线（214）。 这些杆与隔离边缘间隔开一段距离，使得孤立和密集堆积的边缘梯度基本匹配，使得邻近效应变得可忽略。 条的宽度被设定为使得隔离特征的最大自由度范围达到。 还公开了仅对四极照明有效的第二掩模。 该掩模“增加”强度水平，因此适用于较小的方形触点的DOF范围，使得它们接近较大细长触点的强度水平和DOF范围。 增加较小触点中的强度水平可以减少转移到抗蚀剂层时可变尺寸的接触图案之间的临界尺寸差异。 第二掩模包括围绕正方形接触开口设置的称为防散射棒的附加开口。 较小触点的边缘与抗散射条之间的分离量决定了增加强度的量。 防散射条的宽度决定了DOF范围的增加量。 散射棒和防散射棒都被设计成具有明显小于曝光工具的分辨率的宽度，使得它们在光致抗蚀剂曝光期间不产生图案。

公开(公告)号：WO1994027204A2

公开(公告)日：1994-11-24

申请号：PCT/US1994004614

申请日：1994-04-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  HERNDON, William, H.

IPC: G05F03/24

CPC classification number: G05F3/24

Abstract: The present invention describes a bias potential distribution system which provides bias potentials to MOS devices while ensuring the devices' operating conditions remain constant over temperature, process, and power supply fluctuations. Further, bias potentials are generated at one main location within the logic circuit and then distributed throughout the logic circuit to all of the MOS devices or to bias voltage conversion circuits.

Abstract translation: 本发明描述了一种偏置电位分配系统，其向MOS器件提供偏置电位，同时确保器件的工作条件在温度，过程和电源波动上保持恒定。 此外，在逻辑电路内的一个主要位置处产生偏置电位，然后在整个逻辑电路中分布到所有MOS器件或偏置电压转换电路。

公开(公告)号：WO2003021423A2

公开(公告)日：2003-03-13

申请号：PCT/US2002/027970

申请日：2002-09-04

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： HANSEN, Craig ,  BATEMAN, Bruce ,  MOUSSOURIS, John

IPC: G06F7/00

CPC classification number: G06F7/5338 ,  G06F7/4812 ,  G06F7/49994 ,  G06F7/57 ,  G06F7/724 ,  G06F9/30014 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/16 ,  G06F2207/3812 ,  G06F2207/382 ,  G06F2207/3824 ,  G06F2207/3828

Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multipliers regardsless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.

Abstract translation: 本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。 随着操作数大小减小，矩阵和向量操作数的元素数量增加，功能单元完全利用128b乘128b乘法器的全部资源，而不考虑操作数大小。 该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

公开(公告)号：WO1997014094A1

公开(公告)日：1997-04-17

申请号：PCT/US1996016320

申请日：1996-10-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  HANSEN, Craig, C.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F09/302

CPC classification number: G06F9/30189 ,  G06F9/30014 ,  G06F9/3865

Abstract: A floating-point instruction having incorporated floating point information and a method and system for implementing the floating-point instruction in a computer system is described. The floating point information indicates whether an exception trap should occur and the type of rounding to be performed upon "inexact" arithmetic results. The floating point information further indicates whether other floating-point exception traps should occur. This information allows dynamic (e.g. instruction-by-instruction) modification of various operating parameters of the CPU without modifying information in status registers using special instructions or modes, thereby increasing overall CPU performance. The technique is also supported by several mechanisms for providing precise floating-point exceptions.

Abstract translation: 描述了包含浮点信息的浮点指令以及用于在计算机系统中实现浮点指令的方法和系统。 浮点信息指示是否发生异常陷阱，并在“不精确”运算结果时执行舍入的类型。 浮点信息还指示是否应发生其他浮点异常捕获。 该信息允许在不使用特殊指令或模式修改状态寄存器中的信息的情况下对CPU的各种操作参数进行动态（例如逐个指令）修改，从而提高整体CPU性能。 该技术还通过几种提供精确浮点异常的机制来支持。

公开(公告)号：WO1997007451A2

公开(公告)日：1997-02-27

申请号：PCT/US1996013195

申请日：1996-08-14

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  KARZES, Thomas, J. ,  HANSEN, Craig, C. ,  MASSALIN, Henry

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F07/00

CPC classification number: G06F7/762 ,  G06F7/76 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032

Abstract: A method and system for performing arbitrary permutations of sequences of elements. In the general case, the method of the present invention processes the elements to be permuted as a multi-dimensional array, where each element in the array corresponds to one of the elments to be permuted. The permutation is achieved by performing a sequence of sets of permutations, where each set of permutations in the sequence independently permutes the elements within each one-dimensional slice through the array, along some particular dimension of the array. The total number of sets of permutations, or stages, is one less than twice the number of dimensions in the array. An extension to the general method allows some extensions of permutations which involve the copying of individual elements. A system based on the extended general method implements a large class of operations which involve copying and/or permuting elements, where the sequence of elements is a word of data and the elements are bits of data. An efficient control structure for the system permits control signals to be shared across slices of the array. A version of the system based on a two-dimensional array includes three multiplex stages, where the first stage multiplexes along the rows, the second stage multiplexes along the columns, and the third stage multiplexes across the rows once again. Several classes of computer instructions which generally involve the copying and/or permuting of data are also described.

Abstract translation: 一种用于执行元素序列的任意排列的方法和系统。 在一般情况下，本发明的方法将要置换的元素处理为多维阵列，其中阵列中的每个元素对应于待置换的元素中的一个。 通过执行一组排列来实现置换，其中序列中的每组置换通过阵列沿着阵列的某个特定维度独立地排列每个一维切片内的元素。 排列的集合或阶段的总数量是数组中维度数量的两倍。 一般方法的扩展允许一些涉及复制单个元素的排列扩展。 基于扩展通用方法的系统实现涉及复制和/或置换元素的大类操作，其中元素序列是数据字，元素是数据位。 该系统的有效的控制结构允许控制信号在阵列的切片之间共享。 基于二维阵列的系统的版本包括三个复用级，其中第一级沿着行多路复用，第二级沿着列多路复用，并且第三级再次跨越行多路复用。 还描述了通常涉及数据的复制和/或置换的几类计算机指令。

公开(公告)号：WO1996035145A1

公开(公告)日：1996-11-07

申请号：PCT/US1996005224

申请日：1996-04-17

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  WAMPLER, Kurt, E. ,  LAIDIG, Thomas, L.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G03F07/20

CPC classification number: G03F7/70441 ,  G03F1/36 ,  H01J2237/31762 ,  H01J2237/31769

Abstract: A method for synthesizing correction features for an entire mask pattern that initially divides mask pattern data into tiles of data - each tile representing an overlapping section of the original mask pattern. Each of the tiles of data is sequentially processed through correction feature synthesis phases - each phase synthesizing a different type of correction feature. All of the correction features are synthesized for a given tile before synthesizing the correction features for the next tile. Each correction feature synthesis phase formats the data stored in the tile into a representation that provides information needed to synthesize the correction feature for the given phase. Methods for implementing edge bar and serif correction features synthesis phases are also described. The method for synthesizing external type edge bars is performed by oversizing feature data in the tile by an amount equal to the desired spacing of the external edge bar, formatting the oversized data into an edge representation and expanding each of the edges in the edge representation of the oversized data into edge bars having a predetermined width. Internal type of edge bars for the tile are synthesized by initially inverting feature data and then performing the same steps as for generating the external edge bars. The method for serif synthesis is performed by initially formatting tile data into a vertex representation, eliminating certain of the vertices not requiring serifs, synthesizing a positive serif for each convex corner and a negative vertex for each concave corner, and eliminating any disallowed serifs. Internal bars and negative serifs are "cut-out" of original tile data by performing geometric Boolean operations and external bars and positive serifs are concatenated with the "cut-out" tile data, equivalent to performing a geometric OR operation.

Abstract translation: 一种用于将最初将掩模图案数据划分成数据块的整个掩模图案的校正特征的方法，每个图块表示原始掩模图案的重叠部分。 通过校正特征合成阶段顺序地处理每个数据块，每个相合成不同类型的校正特征。 在为下一个瓦片合成修正特征之前，对于给定的瓦片合成所有校正特征。 每个校正特征合成阶段将存储在瓦片中的数据格式化为提供合成给定阶段的校正特征所需的信息的表示。 还描述了实现边缘条和衬里修正特征合成阶段的方法。 用于合成外部边缘条的方法是通过将瓦片中的特征数据超过等于外部边缘条的期望间隔的量来执行的，将大尺寸数据格式化为边缘表示，并且将边缘表示中的每个边缘扩展 超大数据进入具有预定宽度的边条。 通过初始反转特征数据然后执行与产生外边缘条相同的步骤来合成瓦片的边缘条的内部类型。 用于衬线合成的方法是通过将瓦片数据初始格式化为顶点表示，消除某些不需要衬线的顶点，为每个凸角合成一个正衬线和每个凹角的负顶点，以及消除任何不允许的衬线。 内部柱和负衬里是通过执行几何布尔运算和外部柱而将原始瓦片数据“切出”，正衬线与“切出”瓦片数据连接，相当于执行几何或运算。

公开(公告)号：WO1996023364A1

公开(公告)日：1996-08-01

申请号：PCT/US1995012566

申请日：1995-10-12

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CORRY, Alan, G. ,  PURI, Manoj ,  SUTHERLAND, Robert, A.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H04B01/10

CPC classification number: G06K9/0057 ,  G06K9/0051

Abstract: An apparatus and method for decorrelating pairs of mutually contaminated channels in a multi-channel digital signal including two identical data processing paths and a feedback path. Each pair of mutually contaminated channels consists of a first contamined channel and a second contaminated channel. Initially, first and second shifted signals are generated by shifting the original contaminated signal such that the first shifted signal has the first contaminated channel centered at zero frequency and the second shifted signal has the second contaminated channel centered at zero frequency. Each of the first and second shifted signals are coupled to one of the two identical signal processing paths. The first path generates an error corruption component corresponding to the first shifted input signal and subtracts this corruption component from the second shifted signal in order to generate a third decorrelated digital signal. The second path generates an error corruption component corresponding to the second shifted input signal and subtracts it from the first shifted signal in order to generate a fourth decorrelated digital signal. The feedback path generates a current average error correlation factor by multiplying the third and fourth to generate an instantaneous error factor and summing this with the previous average error correlation factor for all samples. The current average error correlation factor is used to generate the first and second error corruption components. Each of the corrupted channels in the original contamined digital signal are decorrelated when the third and fourth digital signals are decorrelated.

Abstract translation: 一种用于在包括两个相同的数据处理路径和反馈路径的多通道数字信号中去相互关联相互污染的通道的装置和方法。 每对相互污染的通道由第一被检测通道和第二污染通道组成。 首先，通过移动原始污染信号来产生第一和第二移位信号，使得第一移位信号具有以零频率为中心的第一污染信道，并且第二移位信号具有以零频率为中心的第二污染信道。 第一和第二移位信号中的每一个耦合到两个相同的信号处理路径之一。 第一路径产生与第一移位输入信号对应的错误损坏部件，并从第二移位信号中减去该损坏部件，以产生第三解相关数字信号。 第二路径产生与第二移位输入信号对应的错误损坏部件，并将其从第一移位信号中减去，以产生第四解相关数字信号。 反馈路径通过乘以第三和第四来产生当前平均误差相关因子以产生瞬时误差因子，并将其与所有样本的先前平均误差相关因子相加。 当前的平均误差相关因子用于产生第一和第二错误损坏组件。 当第三和第四数字信号被去相关时，原始被检查的数字信号中的每个被破坏的信道都被去相关。

公开(公告)号：WO1996003750A1

公开(公告)日：1996-02-08

申请号：PCT/US1995009366

申请日：1995-07-25

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  BATEMAN, Bruce, L.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G11C05/14

CPC classification number: G11C5/143 ,  G11C7/062

Abstract: A circuit for protecting an interconnect line from certain undesirable voltage swings for a given input signal. A transmission gate is coupled in series between the input signal and the interconnect line. The transmission gate's input terminal is coupled to the input signal, its output terminal is coupled to the interconnect line, and its control terminal is coupled to the output of an inverter. The input of the inverter is coupled to the input signal. When the input signal transitions to a voltage that exceeds the trip point of the inverter, the inverter outputs a signal that disables the transmission gate such that the node is isolated from the input signal. A PFET transmission gate is utilized for protection against voltages that are too negative, and an NFET transmission gate is utilized for protection against voltages that are too positive. The inverter may be replaced by a comparator having its positive input coupled to a reference voltage and its negative input coupled to the input signal. The reference voltage determines the trip point of the protection circuit. The protection circuit may also include first and second biased MOS devices (having different channel types) coupled between first and second working potentials. The gate of the first MOS device is coupled to the input signal and the gate of the second MOS device is coupled to the output of the inverter. The MOS devices function as a conductive voltage divider network to establish a voltage on the node when the node is isolated from the input signal.

Abstract translation: 用于保护互连线免于给定输入信号的某些不期望的电压摆动的电路。 传输门串联在输入信号和互连线之间。 传输门的输入端耦合到输入信号，其输出端耦合到互连线，其控制端耦合到逆变器的输出。 反相器的输入耦合到输入信号。 当输入信号转换到超过变频器跳闸点的电压时，变频器输出禁止传输门的信号，使得节点与输入信号隔离。 PFET传输门用于防止太负电压的保护，并且NFET传输门被用于防止过大的电压。 反相器可以由比较器代替，其比较器的正输入耦合到参考电压，其负输入耦合到输入信号。 参考电压确定保护电路的跳变点。 保护电路还可以包括耦合在第一和第二工作电位之间的第一和第二偏置MOS器件（具有不同的沟道类型）。 第一MOS器件的栅极耦合到输入信号，第二MOS器件的栅极耦合到反相器的输出端。 MOS器件用作导电分压器网络，以在节点与输入信号隔离时在节点上建立电压。

公开(公告)号：WO1995005033A1

公开(公告)日：1995-02-16

申请号：PCT/US1994004613

申请日：1994-04-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  WONG, Ban, Pak

IPC: H03K19/018

CPC classification number: H03K19/017563 ,  H03K19/013 ,  H03K19/01831

Abstract: An apparatus for reducing transmisson delay times when transmitting differential signals in an integrated circuit along long interconnect lines (10, 11) includes a current mode line driver which converts the differential signal to be transmitted into a signal that has a relatively low peak-to-peak voltage and large differential current changes. A receiver responsive to differential current changes converts the signal back into an output differential signal having peak-to-peak voltages adaptable to subsequent logic stages. A feedback circuit (Q5, Q6) coupled to the interconnect lines (10, 11) and the receiver functions to clamp the interconnect lines (10, 11) to a predetermined voltage while allowing the output differential signal to have peak-to-peak voltages greater than the predetermined voltage.

Abstract translation: 一种用于在沿着长互连线（10,11）的集成电路中传输差分信号时减小透射延迟时间的装置包括：电流模式线驱动器，其将待传输的差分信号转换成具有相对低的峰 - 峰值电压和大差分电流变化。 响应于差分电流变化的接收器将信号反馈回具有适应于后续逻辑级的峰 - 峰电压的输出差分信号。 耦合到互连线（10,11）的反馈电路（Q5，Q6）和接收器用于将互连线（10,11）钳位到预定电压，同时允许输出差分信号具有峰 - 峰电压 大于预定电压。

公开(公告)号：WO1994005085A1

公开(公告)日：1994-03-03

申请号：PCT/US1993005106

申请日：1993-05-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  WONG, Ban, Pak

IPC: H03K19/0944

CPC classification number: H03K19/018521 ,  H03K19/00361 ,  H03K19/0136 ,  H03K19/017518

Abstract: An ECL-to-CMOS level translator and BiCMOS buffer are described. The current supplied from the first input PMOS transistor (P1) is the input current to a current mirror comprising the first and second NMOS transistors (N1 and N2). The current mirror controls the current sourcing and sinking capability of the translator. Third and fourth NMOS transistors (N3 and N4) are coupled to the first and second NMOS transistors in the current mirror and function to vary the source-to-body voltage of the first and second NMOS transistors and consequently their gain which results in increased current drive and sinking capability. The BiCMOS differential buffer of the present invention provides a differential output signal on first and second output nodes (115 and 215). It is comprised of first and second cross-coupled buffers (100B and 200B). Cross-coupling the buffers results in improved high-to-low transition times.

Abstract translation: 描述了ECL到CMOS电平转换器和BiCMOS缓冲器。 从第一输入PMOS晶体管（P1）提供的电流是包括第一和第二NMOS晶体管（N1和N2）的电流镜的输入电流。 当前镜像控制翻译器的当前采样和下载功能。 第三和第四NMOS晶体管（N3和N4）耦合到电流镜中的第一和第二NMOS晶体管，并且用于改变第一和第二NMOS晶体管的源极体电压，并因此改变其增益，从而导致电流增加 驱动和下沉能力。 本发明的BiCMOS差分缓冲器在第一和第二输出节点（115和215）上提供差分输出信号。 它由第一和第二交叉耦合缓冲器（100B和200B）组成。 交叉耦合缓冲区导致改进的高到低的转换时间。