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    HYBRID MEMS RF SWITCH AND METHOD OF FABRICATING SAME
    44.
    发明申请
    HYBRID MEMS RF SWITCH AND METHOD OF FABRICATING SAME 审中-公开
    混合MEMS射频开关及其制造方法

    公开(公告)号：WO2010072431A1

    公开(公告)日：2010-07-01

    申请号：PCT/EP2009/063495

    申请日：2009-10-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  STAMPER, Anthony ,  LINDGREN, Peter, James

    Inventor： STAMPER, Anthony ,  LINDGREN, Peter, James

    IPC: H01H59/00 ,  B81C1/00

    CPC classification number: B81B3/0097 ,  B81C1/0015 ,  H01H59/0009 ,  Y10T29/49105

    Abstract: Structures having a hybrid MEMS RF switch and method of fabricating such structures using existing wiring layers of a device is provided. The method of manufacturing a MEMS switch includes forming a forcing electrode from a lower wiring layer of a device and forming a lower electrode from an upper wiring layer of the device. The method further includes forming a flexible cantilever arm over the forcing electrode and the lower electrode such that upon application of a voltage to the forcing electrode, the flexible cantilever arm will contact the lower electrode to close the MEMS switch.

    Abstract translation: 提供具有混合MEMS RF开关的结构和使用设备的现有布线层制造这种结构的方法。 制造MEMS开关的方法包括从器件的下布线层形成强制电极，并从器件的上布线层形成下电极。 该方法还包括在强制电极和下电极上形成柔性悬臂，使得在对强制电极施加电压时，柔性悬臂将接触下电极以闭合MEMS开关。

    METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY
    45.
    发明申请
    METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY 审中-公开
    选择性反向掩模平面化和互连结构的方法

    公开(公告)号：WO2010060890A1

    公开(公告)日：2010-06-03

    申请号：PCT/EP2009/065696

    申请日：2009-11-24

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  HE, Zhong-Xiang ,  STAMPER, Anthony ,  WHITE, Jeffrey, Eric

    Inventor： HE, Zhong-Xiang ,  STAMPER, Anthony ,  WHITE, Jeffrey, Eric

    IPC: H01L21/768 ,  H01L21/3105

    CPC classification number: H01L23/528 ,  H01L21/31056 ,  H01L21/76819 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer (30) on a top surface of multiple conductive features (10), (20) and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer (42) is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

    Abstract translation: 用于平坦化诸如电介质的材料层的平面化方法以及通过平面化方法形成的互连结构。 该方法包括在多个导电特征（10），（20）的顶表面和导电特征之间的衬底的顶表面上沉积第一介电层（30）。 第一电介质层的一部分从至少一个导电特征的顶表面选择性地去除，而不去除导电特征之间的第一介电层的一部分。 第二电介质层（42）形成在至少一个导电特征的顶表面上和第一电介质层的顶表面上，并且第二介电层的顶表面被平坦化。 作为蚀刻停止件操作的层位于导电特征中的至少一个的顶表面和第二介电层之间。

    METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS
    46.
    发明申请
    METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS 审中-公开
    通过基板VIAS集成的金属接线结构

    公开(公告)号：WO2010017062A1

    公开(公告)日：2010-02-11

    申请号：PCT/US2009/051908

    申请日：2009-07-28

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COLLINS, David, S. ,  JOSEPH, Alvin ,  LINDGREN, Peter, J. ,  STAMPER, Anthony, K. ,  WATSON, Kimball, M.

    Inventor： COLLINS, David, S. ,  JOSEPH, Alvin ,  LINDGREN, Peter, J. ,  STAMPER, Anthony, K. ,  WATSON, Kimball, M.

    IPC: H01L23/522

    CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: An array of through substrate vias (TSVs) (20) is formed through a semiconductor substrate (12) and a contact- via-level dielectric layer (50) thereupon. A metal-wire-level dielectric layer (60) and a line-level metal wiring structure (80) embedded therein are formed directly on the contact-via-level dielectric layer (50). The line-level metal wiring structure (80) includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer (60). In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs (20) to maximize the contact area between the TSVs (20) and the line-level metal wiring structure (80). In another embodiment, a set of cheesing holes overlying an entirety of seams (18) in the array of TSVs (20) is formed to prevent trapping of any plating solution in the seams (19)of the TSVs (20) during plating to prevent corrosion of the TSVs (20)at the seams (19).

    Abstract translation: 穿过衬底通孔（TSV）（20）的阵列通过半导体衬底（12）和接触通过级介电层（50）在其上形成。 直接在接触通路层电介质层（50）上形成金属线层介电层（60）和嵌入其中的线状金属布线结构（80）。 线状金属布线结构（80）包括填充有金属线层介电层（60）的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV（20）阵列的区域的外侧，以最大化TSV（20）和线路级金属布线结构（80）之间的接触面积。 在另一个实施例中，形成了覆盖在TSV（20）阵列中的整个接缝（18）的一组烘干孔，以防止在电镀期间捕获TSV（20）的接缝（19）中的任何电镀溶液以防止 接缝处的TSV（20）的腐蚀（19）。

    THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER
    47.
    发明申请
    THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER 审中-公开
    通过包括插入式灌装机在内的基板

    公开(公告)号：WO2009102741A1

    公开(公告)日：2009-08-20

    申请号：PCT/US2009/033723

    申请日：2009-02-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  LINDGREN, Peter, J. ,  SPROGIS, Edmund, J. ,  STAMPER, Anthony, K. ,  STEIN, Kenneth, J.

    Inventor： LINDGREN, Peter, J. ,  SPROGIS, Edmund, J. ,  STAMPER, Anthony, K. ,  STEIN, Kenneth, J.

    IPC: H01L23/48

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A through substrate (10) via includes an annular conductor layer at a periphery of a through substrate (10) aperture, and a plug layer (24) surrounded by the annular conductor layer. A method for fabricating the through substrate (10) via includes forming a blind aperture within a substrate (10) and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer (20) that does not fill the aperture and plug layer (24) that does fill the aperture. The backside of the substrate (10) may then be planarized to expose at least the planarized conformal conductor layer. (20)

    Abstract translation: 贯穿基板（10）通孔包括在通孔基板（10）的周边的环形导体层和由环形导体层包围的插塞层（24）。 一种用于制造穿透基底（10）通孔的方法，包括在基底（10）内形成盲孔，并且在盲孔内依次形成并随后在盲孔内平坦化形成不填充孔径和塞子层（24）的共形导体层（20） ），其中填充了孔径。 然后可以将衬底（10）的背面平坦化以至少露出平坦化的共形导体层。 （20）

    STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETS
    48.
    发明申请
    STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETS 审中-公开
    紧凑型长通道FET的结构和方法

    公开(公告)号：WO2009061698A1

    公开(公告)日：2009-05-14

    申请号：PCT/US2008/082226

    申请日：2008-11-03

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DORIS, Bruce, B. ,  RADENS, Carl, J. ,  STAMPER, Anthony, K.

    Inventor： DORIS, Bruce, B. ,  RADENS, Carl, J. ,  STAMPER, Anthony, K.

    IPC: H01L29/00

    CPC classification number: H01L29/1037 ,  H01L29/6659 ,  H01L29/66621

    Abstract: A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate (12) in which the at least one FET includes a long channel length and/or a wide channel width (11) and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.

    Abstract translation: 一种紧凑的半导体结构，包括位于半导体衬底（12）的表面之上和之内的至少一个FET，其中所述至少一个FET包括长沟道长度和/或宽沟道宽度（11），以及制造 同样提供。 在一些实施例中，有序的纳米尺寸图案在垂直于电流的方向上取向。 在这样的实施例中，FET具有长的沟道长度。 在其他实施例中，有序的纳米尺寸图案在平行于电流流动的方向上取向。 在这样的实施例中，FET具有宽的通道宽度。 在另一个实施例中，一个有序的纳米尺寸图案在垂直于电流的方向上定向，而另一个有序的纳米尺寸图案在平行于电流的方向上取向。 在这样的实施例中，提供具有长沟道长度和宽沟道宽度的FET。

    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION
    49.
    发明申请
    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION 审中-公开
    在半导体制造中去除蚀刻工艺残留

    公开(公告)号：WO2008091923A2

    公开(公告)日：2008-07-31

    申请号：PCT/US2008/051758

    申请日：2008-01-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HERRIN, Russell, T. ,  LINDGREN, Peter, J. ,  STAMPER, Anthony, K.

    Inventor： HERRIN, Russell, T. ,  LINDGREN, Peter, J. ,  STAMPER, Anthony, K.

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L23/5223 ,  H01L21/02063 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure incl udes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.

    Abstract translation: 半导体结构及其形成方法。 半导体制造方法包括提供结构的步骤。 一种结构包括（a）介电层，（b）掩埋在所述电介质层中的第一导电区域，其中所述第一导电区域包括第一导电材料，和（c）第二导电区域， 介电层，其中第二导电区域包括不同于第一导电材料的第二导电材料。 该方法还包括以下步骤：在电介质层中形成第一孔和第二孔，导致第一和第二导电区域分别通过第一孔和第二孔暴露于周围环境。 然后，该方法还包括将碱性溶剂引入第一孔和第二孔的底壁和侧壁的步骤。

    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS
    50.
    发明申请
    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS 审中-公开
    防止混合定向晶体管充电损坏

    公开(公告)号：WO2007115146A3

    公开(公告)日：2008-04-24

    申请号：PCT/US2007065604

    申请日：2007-03-30

    Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    IPC: H02H9/00

    CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

    Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

    Abstract translation: 芯片包括CMOS结构，该CMOS结构具有布置在半导体衬底（50）的第一区域（24）中的与衬底的下方体区（18）导电连通的体装置（20），第一区域（24）和 该体区域（20）具有第一晶体取向。 SOI器件（10）设置在绝缘体上半导体（“SOI”）层（14）中，所述绝缘体上半导体（SOI）层通过掩埋介电层（16）与衬底的体区分开，SOI层具有与 第一个晶体取向。 在一个示例中，大容量器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，大容量器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与大容量器件的栅极导体（21）导电连通的栅极导体（11）时，除了存在二极管与SOI器件的反向偏置传导通信之外，SOI器件可能会发生充电损坏 地区。 当栅极导体上的电压或SOI器件的源极或漏极区上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导至体区。

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