公开(公告)号：EP1753134A1

公开(公告)日：2007-02-14

申请号：EP05447184.2

申请日：2005-08-12

Applicant: STMicroelectronics Belgium N.V.

Inventor： Capretta, Pietro

IPC: H03H17/06

CPC classification number: H03H17/0621 ,  H03H17/0685

Abstract: A receiver path comprises a means for generating first digitized samples from a received analog signal at a first sampling rate, e.g. an ADC (12). An interpolating filter (13) is used to generate from the first digitized samples second digitized samples which are estimates of samples obtainable by sampling the received analog signal at a second sample rate lower than the first sampling rate, second digitized samples being output at the first sampling rate and including at least one unusable sample. A circuit (14) is provided for generating a signal for controlling components of the receive path downstream of the interpolation filter to prevent processing of the unusable sample. The advantage of this arrangement is that a separate oscillator at the second sampling rate is not required while still allowing the second sampling rate to be a whole multiple of 1MHz.

Abstract translation: 一种接收机路径包括用于以第一采样速率产生从接收到的模拟信号的第一数字化样本，E.G. 到ADC（12）。 率在插滤波器（13）用于从所述第一数字化样本生成第二数字化样本哪些样品可获得的估计通过以第二采样率比所述第一采样下，第二数字化取样被输出以第一取样接收的模拟信号 采样率和包括至少一个不可用的样品。 一种电路（14）被设置用于产生一个信号，用于控制内插过滤器下游的接收路径的部件，以防止样品的不可用的处理。 这种布置的优点是没有在所述第二采样率一个独立的振荡器，而静静地允许所述第二采样率是1兆赫的整数倍不是必需的。

公开(公告)号：EP1753133A1

公开(公告)日：2007-02-14

申请号：EP05447183.4

申请日：2005-08-12

Applicant: STMicroelectronics Belgium N.V.

Inventor： Capretta, Pietro

IPC: H03H17/06

CPC classification number: H03H17/0621 ,  H03H17/0685

Abstract: A receive path in a receiver comprises means for deriving a first stream of first digitized samples from a received analog signal at a first sampling rate (12), and at least one interpolating filter (32,34,36) in parallel with the first stream of first digitized samples for generating at least a second stream of digitized samples at the first sampling rate but offset with respect to the first stream by a fraction of a sample time period from the first stream. This provides the advantage that a higher sample granularity can be obtained without increasing the sample rate.

Abstract translation: 接收机中的接收路径包括用于以第一采样率（12）从接收到的模拟信号导出第一数字化样本的第一流的装置，以及与第一流并行的至少一个内插滤波器（32,34,36） 第一数字化样本，用于以第一采样率产生至少第二数字化样本流，但是相对于第一流偏移来自第一流的采样时间段的一小部分。 这提供了在不增加采样率的情况下可以获得更高的样品粒度的优点。

公开(公告)号：EP1638282A1

公开(公告)日：2006-03-22

申请号：EP04077552.0

申请日：2004-09-15

Applicant: STMicroelectronics Belgium N.V.

Inventor： Latte, Olivier Rene Nicolas

IPC: H04L27/00 ,  H04B1/58

CPC classification number: H04L27/0002 ,  H03F3/45475 ,  H03F2200/541 ,  H04B1/581 ,  H04L27/2601

Abstract: A line driver circuit (250) couples a data transceiver (210,220) to a line (230). The line driver (250) comprises a differential amplifier (OA1,OA2) which receives a signal for transmission on the line. First and second feedback paths (Z1) connect between outputs of the amplifier and inputs of the amplifier. A bridge (260) couples the differential amplifier (OA1,OA2) to the line (230). The bridge comprises two matching impedance and two secondary transformer winding. Each matching impedance is connected in series with a secondary transformer winding between the outputs of the amplifiers. Two feedback branches connect between tap-points part-way along the secondary windings (262 and 261) and the inputs of the differential amplifier. The line driver circuit (250) shows low sensitivity to accuracy of component values while providing an increased dynamic on the line for a given dynamic of the transceiver and a given attenuation of the received signal.

Abstract translation: 线路驱动器电路（250）将数据收发器（210,220）耦合到线路（230）。 线路驱动器（250）包括差分放大器（OA1，OA2），其接收用于在线路上传输的信号。 第一和第二反馈路径（Z1）连接放大器的输出和放大器的输入。 桥（260）将差分放大器（OA1，OA2）耦合到线路（230）。 该桥包括两个匹配阻抗和两个次级变压器绕组。 每个匹配阻抗与放大器输出端之间的次级变压器绕组串联。 两个反馈支路沿着次级绕组（262和261）和差分放大器的输入端分接点之间连接。 线路驱动器电路（250）对分量值的精度显示低灵敏度，同时在给定的收发器动态线路上提供增加的动态以及接收信号的给定衰减。

公开(公告)号：EP1638210A1

公开(公告)日：2006-03-22

申请号：EP04077551.2

申请日：2004-09-15

Applicant: STMicroelectronics Belgium N.V.

Inventor： Borremans, Marc ,  Goetschalckx, Paul ,  Monterastelli, Andrea

IPC: H04B1/04 ,  H03D7/16 ,  H03C3/40

CPC classification number: H03J1/005 ,  H04B2001/0491

Abstract: An RF transmitter suitable for ISM band transmissions has an IF modulator (120) and an RF modulator (150), the IF modulator being arranged to use a very-low-IF-frequency f IF , smaller than half the channel bandwidth, such that spurious unwanted modulation components fall in other channels having a channel number within one or two of a channel being transmitted. This can reduce the VCO pulling problem and reduce adjacent channel power degradation compared to using higher IF frequencies. The local oscillator PLL's fractionality is used in order to optimize the adjacent power frequency plan by selecting the most appropriate IF frequency. For the "Bluetooth ® Wireless Technology" application, the IF frequency is

Abstract translation: 适用于ISM频带传输的RF发射机具有IF调制器（120）和RF调制器（150），IF调制器被配置为使用小于信道带宽一半的非常低的IF频率f IF，使得 杂散的不需要的调制分量落在其它信道中，其中信道号正在传输的信道的一个或两个之内。 与使用较高的IF频率相比，这可以减少VCO牵引问题并降低相邻信道功率的降低。 使用本地振荡器PLL的分数，以通过选择最合适的IF频率来优化相邻功率频率计划。 对于“蓝牙®无线技术”应用，IF频率<500kHz，主要无滤波杂散分量（1LO.xBB，x：-3，-2，...，+ 3）图像，载波， 对于0和1个FM信号，拉动被定位在相邻信道的频带中。

公开(公告)号：EP1422826B1

公开(公告)日：2006-02-22

申请号：EP02447227.6

申请日：2002-11-21

Applicant: STMicroelectronics Belgium N.V.

Inventor： Craninckx, Jan Frans Lucien

IPC: H03L7/18 ,  H03L7/099 ,  H03L7/089

CPC classification number: H03L7/0996 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/18

公开(公告)号：EP1596266A1

公开(公告)日：2005-11-16

申请号：EP04447121.7

申请日：2004-05-14

Applicant: STMicroelectronics Belgium N.V.

Inventor： Himpe, Vincent

IPC: G05F1/56

CPC classification number: G05F1/571

Abstract: The present invention is related to a regulator circuit comprising a regulator circuit input and a regulator circuit output, a regulating element in connection with the regulator circuit input and the regulator circuit output, and a control circuit arranged for being fed with a signal related to the regulator circuit output. The regulator circuit further comprises a safety detector arranged for being fed with the signal related to the regulator circuit output. The safety detector is further arranged to control a switch, being in connection with the control circuit's output and with the regulating element.

Abstract translation: 本发明涉及一种调节器电路，其包括调节器电路输入和调节器电路输出，与调节器电路输入和调节器电路输出相关的调节元件，以及控制电路，被配置为馈送与 稳压电路输出。 调节器电路还包括安全检测器，安全检测器被布置为馈送与调节器电路输出相关的信号。 安全检测器还被布置成控制与控制电路的输出和调节元件相关的开关。

公开(公告)号：EP1548932A1

公开(公告)日：2005-06-29

申请号：EP03079182.6

申请日：2003-12-24

Applicant: STMicroelectronics Belgium N.V.

Inventor： Joos, Dieter ,  Borremans, Marc

IPC: H03F3/45

CPC classification number: H03F3/45179 ,  H03F3/189 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45306 ,  H03F2203/45318

Abstract: A low noise differential amplifier has a pair of single ended common-gate or common-base circuits and cross coupling of an input of one of the pair to the gate or base of the other one of the pair. This cross-coupling puts the differential input voltage over the Gate-Source of the common-gate transistor (or Base-Emitter of the common base transistor). This means that the same input impedance and gain can be made with half the current compared to a basic common-gate topology. The cross-coupling means the noise generated by the positive side of the common-gate structure ends up partly on the negative output and vice versa, and so the Noise Figure can be less than 3dB.

Abstract translation: 低噪声差分放大器具有一对单端公共栅极或公共基极电路，并且该对中的一个的输入与该对中的另一个的栅极或基极交叉耦合。 这种交叉耦合将差分输入电压放在公共栅极晶体管（或公共基极晶体管的基极 - 发射极）的栅极 - 源极上。 这意味着与基本公共门拓扑相比，可以以一半的电流进行相同的输入阻抗和增益。 交叉耦合意味着由共栅结构的正侧产生的噪声部分地在负输出端反而相反，因此噪声系数可以小于3dB。

公开(公告)号：EP1545007A1

公开(公告)日：2005-06-22

申请号：EP04447281.9

申请日：2004-12-17

Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM ( IMEC) ,  STMicroelectronics Belgium N.V.

Inventor： Craninckx, Jan Frans Lucien

IPC: H03L7/081 ,  H03D3/00 ,  H03B27/00

CPC classification number: H03B27/00 ,  H03D7/18 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/16

Abstract: The present invention is related to a device for generating signals spaced π/X rad apart (X being an integer) comprising

at least one delay cell (15) with a delay approximately corresponding to a phase shift π/X rad, and
at least one phase detection system (16) inputting at least two signals (10) delayed by π/2 rad with respect to one another by the delay cell(s) (15) and generating a feedback signal (18) to at least one delay cell (15).

Abstract translation: 本发明涉及用于产生间隔π/ X辐射（X是整数）的信号的装置，该装置包括延迟大约对应于相移π/ X弧的至少一个延迟单元（15），以及至少一个 相位检测系统（16）通过延迟单元（15）相对于彼此输入延迟π/ 2弧度的至少两个信号（10）并且产生反馈信号（18）到至少一个延迟单元 15）。

公开(公告)号：EP1536599A1

公开(公告)日：2005-06-01

申请号：EP03078716.2

申请日：2003-11-26

Applicant: STMicroelectronics Belgium N.V.

Inventor： Van Parys, Jorgen

IPC: H04L12/56

CPC classification number: H04W74/04 ,  H04W74/06 ,  H04W84/18 ,  Y02D70/144 ,  Y02D70/25

Abstract: A Bluetooth master radio frequency unit (20) addresses a slave radio frequency unit, to enable the slave to resynchronize to the master, by sending poll packets or null packets, the master being arranged to send sufficient null packets to enable the slave to resynchronize, before sending a poll packet, to determine whether the slave has resynchronized. This approach can provide the slave with the same number of synchronization packets as in the simpler algorithms, while allowing the slave to preserve more (transmit) power and still allowing the master to detect whether the slave has resynchronized or not (and thus to update a Link Supervision Timer for example). Notably this is also suitable for use in prescheduling implementations.

Abstract translation: 蓝牙主机射频单元（20）寻址从射频单元，以使从机能够通过发送轮询分组或空分组来重新同步主机，主机被安排为发送足够的空分组以使从机重新同步， 在发送轮询数据包之前，确定从站是否已重新同步。 这种方法可以为从属设备提供与更简单的算法相同数量的同步数据包，同时允许从器件保留更多（发送）功率，并且还允许主器件检测从器件是否已重新同步（从而更新 Link监控定时器）。 值得注意的是，这也适用于预调节实现。

公开(公告)号：EP1531591A1

公开(公告)日：2005-05-18

申请号：EP03078543.0

申请日：2003-11-11

Applicant: STMicroelectronics Belgium N.V.

Inventor： Aerts, Wouter ,  Hug, Roland

IPC: H04L27/26 ,  H04L27/38

CPC classification number: H04L27/2657 ,  H04L27/3881

Abstract: A signal resampler carries out a time domain interpolation of an input signal for compensating for frequency offset, such as found in an ADSL system. A sample selector interpolator carries out part of the interpolation and a second, e.g. polynomial interpolator carries out the rest of the interpolation. The time interval between samples being interpolated, can be effectively divided between sample selector interpolator and a small second, e.g. polynomial interpolator. The complexity of the second, e.g. polynomial interpolator can be reduced or its accuracy increased if it is effectively interpolating over a much smaller time interval. The sample selector interpolator can be an oversampling arrangement, and enable the order of the second, e.g. polynomial interpolator to be reduced. Selected ones of the oversampled samples are fed to the second, e.g. polynomial interpolator to keep the operating frequency lower. A chain of upsamplers can be used to generate the oversampled samples.

Abstract translation: 信号重采样器执行输入信号的时域内插以补偿频偏，例如在ADSL系统中发现的。 采样选择器内插器执行一部分内插，而第二个例如内插器执行内插。 多项式内插器执行其余的内插。 被插值的样本之间的时间间隔可以在样本选择器内插器与小的秒之间有效地分配。 多项式插值器。 第二个的复杂性，例如 多项式内插器如果在更小的时间间隔内进行有效内插，则可以减少或提高其精度。 采样选择器内插器可以是一个过采样装置，并且可以启用第二个采样选择器的顺序。 多项式内插器被减少。 将选定的一些过采样样本馈送到第二个例如 多项式内插器保持工作频率更低。 一系列上采样器可用于生成过采样采样。