公开(公告)号：US09379072B2

公开(公告)日：2016-06-28

申请号：US14552186

申请日：2014-11-24

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu ,  Ying-Nan Wen

IPC: H01L31/00 ,  H01L23/00 ,  H01L25/00 ,  H01L27/146

CPC classification number: H01L24/09 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/24051 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/8385 ,  H01L2224/92133 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14335 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second substrate is attached onto a second side opposite to the first side of the first substrate. The second substrate includes a micro-electric element and has a plurality of second conductive pads corresponding to the plurality of first conductive pads, disposed on a first side of the second substrate and between the first substrate and the second substrate. A redistribution layer is disposed on a second side opposite to the first side of the second substrate. The redistribution layer penetrates the second substrate, second conductive pads and the first substrate and extends into the first conductive pads to electrically connect the first and second conductive pads.

Abstract translation: 提供了包括第一基板的芯片封装。 多个第一导电焊盘设置在第一基板的第一侧上。 第二基板附接到与第一基板的第一侧相对的第二侧。 第二基板包括微电元件，并且具有多个与多个第一导电焊盘相对应的第二导电焊盘，该第二导电焊盘设置在第二基板的第一侧上且位于第一基板和第二基板之间。 再分配层设置在与第二基板的第一侧相对的第二侧上。 再分配层穿透第二基板，第二导电焊盘和第一基板并延伸到第一导电焊盘中以电连接第一和第二导电焊盘。

公开(公告)号：US20160141254A1

公开(公告)日：2016-05-19

申请号：US15008202

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Yi-Min LIN ,  Yi-Ming CHANG ,  Shu-Ming CHANG ,  Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Ming CHENG

IPC: H01L23/552 ,  H01L23/544 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2223/5446 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/451 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 布置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中的导线层; 位于所述导线层和所述半导体基板之间的绝缘层; 以及设置在所述第一表面上并且具有至少一个孔的金属遮光层，其中所述至少一个孔的形状是四边形。

公开(公告)号：US20160141219A1

公开(公告)日：2016-05-19

申请号：US15008241

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/48 ,  G06K9/00 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11 ,  H05K3/32 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/3192 ,  G01L19/0061 ,  G01L19/06 ,  G01L19/14 ,  G06F21/32 ,  G06K9/00 ,  G06K9/00006 ,  H01L21/0212 ,  H01L21/02263 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/525 ,  H01L2021/60022 ,  H01L2224/11 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/181 ,  H05K3/32

Abstract: A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad.

Abstract translation: 芯片封装包括芯片，阻挡层，永久粘合剂层，支撑体，缓冲层，再分配层，钝化层和导电结构。 芯片的导电焊盘和感测装置位于芯片的基板的第一表面上，并且导电焊盘从基板的侧表面突出。 坝层围绕感测装置。 永久性粘合剂层位于载体和基底之间。 支撑体和永久粘合剂层具有暴露导电垫的沟槽。 缓冲层位于支架上。 再分配层位于缓冲层上，在支撑体上，永久性粘合剂层和导电垫面对沟槽。 钝化层覆盖再分配层，缓冲层和导电焊盘。

公开(公告)号：US09334156B2

公开(公告)日：2016-05-10

申请号：US14747507

申请日：2015-06-23

Applicant: XINTEC INC.

Inventor： Chien-Min Lin ,  Yu-Ting Huang ,  Chen-Ning Fu ,  Yen-Shih Ho

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81C1/00182 ,  B81C1/00269 ,  B81C2201/0197 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package includes a semiconductor chip, an interposer, a polymer adhesive supporting layer, a redistribution layer and a packaging layer. The semiconductor chip has a sensor device and a conductive pad electrically connected to the sensing device, and the interposer is disposed on the semiconductor chip. The interposer has a trench and a through hole, which the trench exposes a portion of the sensing device, and the through hole exposes the conductive pad. The polymer adhesive supporting layer is interposed between the semiconductor chip and the interposer, and the redistribution layer is disposed on the interposer and in the through hole to be electrically connected to the conductive pad. The packaging layer covers the interposer and the redistribution layer, which the packaging layer has an opening exposing the trench.

Abstract translation: 芯片封装包括半导体芯片，插入件，聚合物粘合剂支撑层，再分布层和包装层。 半导体芯片具有传感器装置和与感测装置电连接的导电焊盘，并且插入器设置在半导体芯片上。 插入器具有沟槽和通孔，沟槽暴露感测装置的一部分，并且通孔暴露导电垫。 聚合物粘合剂支撑层插入在半导体芯片和插入件之间，并且再分配层设置在插入件上和通孔中以与导电焊盘电连接。 包装层覆盖插入件和再分配层，其中封装层具有露出沟槽的开口。

公开(公告)号：US20160118506A1

公开(公告)日：2016-04-28

申请号：US14570949

申请日：2014-12-15

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU

IPC: H01L31/0203 ,  H01L35/02 ,  H01L35/34 ,  H01L31/18 ,  H01L31/02

CPC classification number: H01L35/08 ,  G01J5/024 ,  G01J5/045 ,  G01J5/20 ,  H01L21/78 ,  H01L23/053 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/498 ,  H01L24/33 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/1876 ,  H01L35/02 ,  H01L35/10 ,  H01L35/34 ,  H01L2224/11

Abstract: A semiconductor package includes a substrate, at least one support, a cover, and a plate. The substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface. The light sensor or the thermal sensor is disposed on the first surface. The second surface has an opening to expose the light sensor (or the thermal sensor). The support is disposed on the first surface. The cover is disposed on the support, such that the cover is above the light sensor (or the thermal sensor) to form a first space between the cover and the light sensor (or the thermal sensor). The plate is placed on the second surface to cover the opening, such that a second space is formed between the plate and the light sensor (or the thermal sensor).

Abstract translation: 半导体封装包括基板，至少一个支撑件，盖板和板。 衬底具有至少一个光传感器或热传感器，第一表面和与第一表面相对的第二表面。 光传感器或热传感器设置在第一表面上。 第二表面具有露出光传感器（或热传感器）的开口。 支撑件设置在第一表面上。 盖子设置在支撑件上，使得盖子在光传感器（或热传感器）上方，以在盖和光传感器（或热传感器）之间形成第一空间。 板被放置在第二表面上以覆盖开口，使得在板和光传感器（或热传感器）之间形成第二空间。

公开(公告)号：US20160111555A1

公开(公告)日：2016-04-21

申请号：US14971395

申请日：2015-12-16

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Shu-Ming CHANG ,  Po-Han LEE

IPC: H01L31/0203 ,  H01L31/02 ,  H01L31/18

CPC classification number: H01L31/0203 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/13 ,  H01L31/02005 ,  H01L31/18 ,  H01L2224/131 ,  H01L2224/73253 ,  Y02P70/521 ,  H01L2924/014

Abstract: A method of manufacturing chip package includes providing a semiconductor wafer having a plurality of semiconductor chips. An outer spacer and a plurality of inner spacers are formed on the semiconductor wafer. A protection lid is formed and disposed on the outer spacer and the inner spacers. A plurality of cavities is formed on each of the semiconductor chips from a lower surface thereof to expose the conductive pad disposed on the upper surface of the semiconductor chip. A plurality of conductive portions is formed and fills each of the cavities and electrically connected to each of the conductive pads. A plurality of solder balls is disposed on the lower surface and electrically connected to each of the conductive portions. The semiconductor chips are separated by cutting along a plurality of cutting lines between each of the semiconductor chips.

Abstract translation: 制造芯片封装的方法包括提供具有多个半导体芯片的半导体晶片。 在半导体晶片上形成有外隔离物和多个内隔离物。 保护盖形成并设置在外隔离件和内间隔件上。 从其下表面在每个半导体芯片上形成多个空腔，以露出设置在半导体芯片的上表面上的导电焊盘。 形成多个导电部分，并填充每个空腔并电连接到每个导电焊盘。 多个焊球设置在下表面并电连接到每个导电部分。 半导体芯片通过沿着每个半导体芯片之间的多个切割线进行切割来分离。

公开(公告)号：US20160099195A1

公开(公告)日：2016-04-07

申请号：US14877806

申请日：2015-10-07

Applicant: XINTEC INC.

Inventor： Yu-Lung HUANG

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  B81B7/00 ,  B81C1/00 ,  H01L27/146 ,  H01L25/16

CPC classification number: H01L23/481 ,  B81B7/007 ,  B81C1/00238 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L25/16 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/038 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/0556 ,  H01L2224/05568 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/181 ,  H01L2224/48145 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a conducting pad are adjacent to the upper surface. A through-hole penetrates the first substrate. A redistribution layer extends from the lower surface into the through-hole and is electrically connected to the conducting pad. The redistribution layer further laterally extends from the lower surface to protrude from the sidewall. A method for forming the chip package is also provided.

Abstract translation: 提供了包括具有上表面，下表面和侧壁的第一基板的芯片封装。 感测区域或器件区域和导电焊盘邻近上表面。 通孔贯穿第一基板。 再分配层从下表面延伸到通孔中并且电连接到导电垫。 再分布层从下表面进一步横向延伸以从侧壁突出。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20160052782A1

公开(公告)日：2016-02-25

申请号：US14932814

申请日：2015-11-04

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU

IPC: B81C1/00

CPC classification number: B81C1/00325 ,  B81B2207/092 ,  B81B2207/097 ,  B81C1/00301 ,  B81C2201/0115 ,  B81C2203/0118 ,  H01L21/6835 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/93 ,  H01L2221/68304 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2221/68386 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11009 ,  H01L2224/11019 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15788 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.

Abstract translation: 本发明提供一种电子器件封装及其制造方法。 电子装置封装包括传感器芯片。 传感器芯片的上表面包括感测膜。 具有开口结构的覆盖板覆盖传感器芯片的上表面。 覆盖板和传感器芯片之间的腔体对应于感测膜的位置，其中空腔与开口结构连通。 间隔件位于覆盖板和传感器芯片之间，围绕腔体。 压力释放区域位于间隔件和感测膜之间。

公开(公告)号：US09214579B2

公开(公告)日：2015-12-15

申请号：US14534684

申请日：2014-11-06

Applicant: XINTEC INC.

Inventor： Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/0232 ,  H01L31/02 ,  H01L31/18 ,  H01L31/0236

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了具有硅衬底和保护层的晶片结构。 保护层上的电焊盘通过硅衬底的凹入区露出。 在硅基板的侧壁上形成隔离层，该隔离层包围该凹陷区域以及该硅基板的远离该保护层的表面。 在隔离层和电焊盘上形成再分布层。 在再分布层上形成钝化层。 图案化钝化层以在其中形成第一开口。 在通过第一开口露出的再分布层上形成第一导电层。 导电结构布置在第一开口中，使得导电结构与第一导电层电接触。

公开(公告)号：US09209124B2

公开(公告)日：2015-12-08

申请号：US13964999

申请日：2013-08-12

Applicant: XINTEC INC.

Inventor： Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/58 ,  H01L23/525 ,  H01L29/06 ,  H01L21/683

CPC classification number: H01L23/585 ,  H01L21/283 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/525 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/1302 ,  H01L2224/131 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括具有第一表面和与其相对的第二表面的半导体衬底。 导电垫位于第一表面上。 侧凹部位于半导体衬底的至少第一侧上，其中侧凹部从第一表面朝向第二表面延伸并跨越第一侧的整个长度。 导电层位于第一表面上并电连接到导电焊盘，其中导电层延伸到侧凹槽。