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公开(公告)号：KR1020030095442A
公开(公告)日：2003-12-24
申请号：KR1020020032341
申请日：2002-06-10
Applicant: 삼성전자주식회사
IPC: G06F17/50
CPC classification number: G06F17/5036
Abstract: PURPOSE: A method for classifying aggressors for analyzing cross-talk of a circuit is provided to reduce the time required for classification of the aggressors by executing backwards search to a circuit where a common net exist. CONSTITUTION: A CNF(Conjunction Normal Form) clauses are classified to a victim and an aggressor(100). Backwards search is executed from signal lines of the victim and aggressor(110). It is judged whether a common net exists(120). If not, the aggressor is assumed as a true aggressor, and the aggressor classification is stopped(130). Otherwise, the obtained CNF clauses are added up from a signal line of the victims to a signal line where the common net exists, and the obtained CNF clauses are added up from a signal line of the aggressor to the signal line where the common net exists(140). Other CNF clauses of each case are obtained in differing signal values of the victim and the aggressor(150). BDD(Binary Decision Diagrams) related to the obtained CNF clauses are obtained(160). If a result of the CNF clauses by the reduced BDD is 1(170), the aggressor is judged as a false aggressor(180). Otherwise, the aggressor is judged as a true aggressor(190).
Abstract translation: 目的：提供一种用于分类攻击者分析电路串扰的方法，以通过向存在共同网络的电路执行向后搜索来减少攻击者分类所需的时间。 宪法：CNF（Conjunction Normal Form）条款被分类为受害者和侵略者（100）。 向后搜索是从受害者和侵略者的信号线（110）执行的。 判断是否存在共同的网络（120）。 如果不是，侵略者被认为是真正的侵略者，并且侵略者分类被停止（130）。 否则，所获得的CNF条款从受害者的信号线相加到共同网络的信号线，并且所获得的CNF条款从侵略者的信号线加到存在公共网络的信号线 （140）。 每个案件的其他CNF条款是以受害者和侵略者的不同信号值（150）获得的。 获得与获得的CNF条款相关的BDD（二进制决策图）（160）。 如果通过减少BDD的CNF条款的结果是1（170），则侵略者被判断为虚假的侵略者（180）。 否则，侵略者被判定为真正的侵略者（190）。
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公开(公告)号：KR1020020033953A
公开(公告)日：2002-05-08
申请号：KR1020000064218
申请日：2000-10-31
Applicant: 삼성전자주식회사
IPC: G11C7/06
CPC classification number: H03K3/356113 , G11C7/065 , G11C2207/063
Abstract: PURPOSE: A current sense amplifier circuit of a semiconductor memory device is provided, which improves an operation speed by increasing an amplification, and maintains a stability as to an increase of a power supply voltage. CONSTITUTION: PMOS transistors(MP31, MP32) has a structure where input ports(IN,INB) are connected to each source and gates and drains are connected cross coupled. That is, the PMOS transistors are sense transistors having a latch structure and sense inputted current difference. The input ports are connected data input/output line pair. Drains of each PMOS transistor are connected to an output port(OUT) and an inversion output port(OUTB). NMOS transistors(MN31,MN32) are load transistors operating as load resistors respectively, and have a diode structure where their gates and drains are connected to the drains of the PMOS transistors. The NMOS transistors receives currents(I1,I2) applied as input data through each PMOS transistor, and the output voltages are varied according to the supplied current. A latch(30) is connected with the NMOS transistors in parallel, and forms another current path from the PMOS transistors, in response to a bias voltage(BIAS). A bias circuit(32) activates or inactivates the bias voltage in response to a control signal.
Abstract translation: 目的：提供半导体存储器件的电流检测放大器电路，其通过增加放大来提高操作速度，并且保持对电源电压的增加的稳定性。 构成：PMOS晶体管（MP31，MP32）具有输入端口（IN，INB）连接到每个源极的结构，栅极和漏极连接成交叉耦合。 也就是说，PMOS晶体管是具有锁存结构和感测输入电流差的读出晶体管。 输入端口连接数据输入/输出线对。 每个PMOS晶体管的漏极连接到输出端口（OUT）和反相输出端口（OUTB）。 NMOS晶体管（MN31，MN32）是分别作为负载电阻器工作的负载晶体管，并且具有二极管结构，其栅极和漏极连接到PMOS晶体管的漏极。 NMOS晶体管接收通过每个PMOS晶体管作为输入数据施加的电流（I1，I2），并且输出电压根据所提供的电流而变化。 锁存器（30）与NMOS晶体管并联连接，并响应于偏置电压（BIAS）从PMOS晶体管形成另一电流路径。 偏置电路（32）响应于控制信号激活或者使偏置电压失效。
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