公开(公告)号：KR1020040035065A

公开(公告)日：2004-04-29

申请号：KR1020020063789

申请日：2002-10-18

Applicant: 삼성전자주식회사

Inventor： 임규남

IPC: G11C5/14

CPC classification number: H03K17/223

Abstract: PURPOSE: A power up signal generator is provided to generate a power up signal stably without regard to temperature variation, and to operate stably at a low power supply voltage by lowering a trip voltage. CONSTITUTION: According to the power up signal generator, a PMOS transistor(50) supplies a power supply voltage dropped to a node(N1) above a set voltage as a power supply voltage increases after an initial power supply voltage is supplied. A current source(54) flows a constant current by receiving the power supply voltage supplied from the PMOS transistor. The first inverter(60) inverts the voltage level supplied from the PMOS transistor to the node(N1) when the voltage level reaches a threshold voltage while a constant reference current flows from the current source. And the second inverter(62) outputs a power up signal by delaying an inverted output signal from the first inverter and then inverting it.

Abstract translation: 目的：提供上电信号发生器，以稳定地产生上电信号，而不考虑温度变化，并通过降低跳闸电压在低电源电压下稳定工作。 构成：根据上电信号发生器，在提供初始电源电压之后，随着电源电压增加，PMOS晶体管（50）向落下的节点（N1）提供高于设定电压的电源电压。 电流源（54）通过接收从PMOS晶体管提供的电源电压来流过恒定电流。 当电压电平达到阈值电压时，第一反相器（60）将从PMOS晶体管提供的电压电平反转到节点（N1），同时恒定的参考电流从电流源流出。 并且第二反相器（62）通过延迟来自第一反相器的反相输出信号然后将其反相来输出上电信号。

公开(公告)号：KR100380344B1

公开(公告)日：2003-04-14

申请号：KR1020000046232

申请日：2000-08-09

Applicant: 삼성전자주식회사

Inventor： 임규남 ,  최종현 ,  강상석

IPC: G01R31/28

CPC classification number: G11C29/56 ,  G01R31/319

Abstract: An apparatus and a method are disclosed for package level burn-in test circuit in semiconductor devices. The apparatus includes a package burn-in register, a test voltage generator for the package level burn-in test, a burn-in master signal generator, and a burn-in test circuit. The package burn-in register stores a package burn-in set-order from the outside and generates a package burn-in set-signal. The test voltage generator generates burn-in test voltages in response to the package burn-in set-signal and to address signals through first address terminals from the outside. The burn-in master signal generator generates a burn-in master signal by combining and receiving the second address signal form first address terminals, a wafer burn-in enable signal from a control signal input terminal, and the package burn-in set-signal. After receiving the burn-in master signal, multiple address signals from multiple third address terminals, and the test voltages for the package level burn-in test, the burn-in test circuit performs a package level burn-in test.

Abstract translation: 公开了一种用于半导体器件中的封装级老化测试电路的设备和方法。 该设备包括封装老化寄存器，用于封装级老化测试的测试电压发生器，老化主信号发生器和老化测试电路。 封装老化寄存器存储来自外部的封装老化设置顺序，并生成封装老化设置信号。 测试电压发生器响应于封装老化设置信号产生老化测试电压并通过来自外部的第一地址端子寻址信号。 老化主信号发生器通过组合和接收来自第一地址端子的第二地址信号，来自控制信号输入端子的晶片老化使能信号和封装老化设置信号来产生老化主信号 。 老化测试电路在接收到老化主信号，来自多个第三地址端子的多个地址信号以及用于封装级老化测试的测试电压之后，执行封装级老化测试。

公开(公告)号：KR1020020088109A

公开(公告)日：2002-11-27

申请号：KR1020010026998

申请日：2001-05-17

Applicant: 삼성전자주식회사

Inventor： 임규남 ,  강상석 ,  장성진

IPC: G11C29/00

CPC classification number: G05F1/465

Abstract: PURPOSE: A semiconductor memory device, a circuit for controlling a voltage level of the device, a circuit for controlling a delay time of the device and methods for the same are provided to improve yields thereof by reforming rejected products as good products by controlling voltage parameters and time parameters at a package level. CONSTITUTION: A circuit for controlling a voltage level of a semiconductor memory device includes a mode setting device(70) for setting states of a first and a second control signals in response to a mode setting command, a program device for being programmed at a package level in response to the first control signal and generating the programmed output signal in response to the second control signal and a pair of switching devices(86-1,86-2) for controlling a voltage level in response to the programmed output signal.

Abstract translation: 目的：提供一种半导体存储器件，用于控制器件的电压电平的电路，用于控制器件的延迟时间的电路及其方法，以通过控制电压参数将废弃产物重整成优质产品来提高其产率 和包级别的时间参数。 构成：用于控制半导体存储器件的电压电平的电路包括：用于响应于模式设置命令设置第一和第二控制信号的状态的模式设置装置（70），用于在封装 电平响应于第一控制信号并响应于第二控制信号产生编程的输出信号;以及一对开关装置（86-1,86-2），用于响应于编程的输出信号控制电压电平。

公开(公告)号：KR1020020069041A

公开(公告)日：2002-08-29

申请号：KR1020010009340

申请日：2001-02-23

Applicant: 삼성전자주식회사

Inventor： 임규남

IPC: G11C7/06

CPC classification number: G11C16/26

Abstract: PURPOSE: A semiconductor memory device and a data read method of the same are provided to generate stable read data by decreasing a loop gain in case an input resistance of a current sense amplifier is negative. CONSTITUTION: A memory cell array includes a plurality of memory cell. A plurality of data input/output line pair are connected with a plurality of local data input/output line pair of the memory cell array. A plurality of first current sense amplification unit(20-1,20-2) control a loop gain in response to a control signal and amplify each current difference of the plurality of data input/output line pair. A current sense amplifier input resistance sensing and loop gain control signal generating unit(22,24) senses an input resistance of the plurality of first current sense amplification unit to generate the control signal in case a read command is permitted.

Abstract translation: 目的：提供半导体存储器件及其数据读取方法，以在电流检测放大器的输入电阻为负的情况下，通过减小环路增益来产生稳定的读数据。 构成：存储单元阵列包括多个存储单元。 多个数据输入/输出线对与存储单元阵列的多个本地数据输入/输出线对连接。 多个第一电流检测放大单元（20-1,20-2）响应于控制信号控制环路增益，并放大多个数据输入/输出线路对中的每个电流差。 在允许读命令的情况下，电流检测放大器输入电阻感测和环路增益控制信号产生单元（22,24）感测多个第一电流检测放大单元的输入电阻以产生控制信号。

公开(公告)号：KR100343380B1

公开(公告)日：2002-07-15

申请号：KR1020000061574

申请日：2000-10-19

Applicant: 삼성전자주식회사

Inventor： 임규남

IPC: G11C5/14

Abstract: 본 발명은 전압 레벨 검출회로 및 이를 이용한 전압 발생회로를 공개한다. 그 회로는 전원전압과 중간 노드사이에 직렬 연결되어 입력되는 고전압에 대응하는 제1전류를 발생하기 위한 제1전류 발생회로, 중간 노드와 접지전압사이에 연결되어 궤환 전압에 대응하는 제2전류를 발생하기 위한 제2전류 발생회로, 중간 노드의 전압과 기준전압의 차를 증폭하여 궤환 전압을 발생하기 위한 차동 증폭회로, 및 궤환 전압을 반전하고 버퍼하여 전압 검출신호를 발생하기 위한 인버터로 구성되어 있다. 따라서, 전압 레벨 검출회로의 트립 전압이 공정 변화에 의해서 변화되더라도 궤환 출력전압의 레벨의 변화가 거의 없는 안정적인 전압을 발생할 수 있다.

公开(公告)号：KR1020020030583A

公开(公告)日：2002-04-25

申请号：KR1020000061574

申请日：2000-10-19

Applicant: 삼성전자주식회사

Inventor： 임규남

IPC: G11C5/14

CPC classification number: G05F3/242 ,  G11C5/143 ,  G11C5/145

Abstract: PURPOSE: A voltage level detecting circuit and a voltage generating circuit using the same is provided to stabilize a fed-back voltage level although a voltage detection level is varied according to process variation, and to improve an operating speed by reducing a variation width of the fed-back voltage. CONSTITUTION: A PMOS transistor(M5) and an NMOS transistor(N11) are connected in series between an internal power supply voltage(VINT) and a node(F), and have their gates connected to receive a high voltage(VPP) respectively. An NMOS transistor(N12) is connected between the node(F) and a ground voltage, and has a gate connected to receive a voltage(Vout1). A differential amplifier(AMP1) amplifies a difference between a reference voltage(Vref) and a voltage of the node(F), and generates the voltage(Vout1). An inverter(I13) receives the voltage(Vout1) to generate a high voltage detection signal(VPPS).

Abstract translation: 目的：提供电压电平检测电路和使用该电压电平检测电路的电压产生电路，以稳定反馈电压电平，尽管电压检测电平根据工艺变化而变化，并且通过减小电压检测电路的变化宽度来提高操作速度 反馈电压。 构成：PMOS晶体管（M5）和NMOS晶体管（N11）串联连接在内部电源电压（VINT）和节点（F）之间，并且其栅极分别连接以接收高电压（VPP）。 NMOS晶体管（N12）连接在节点（F）和接地电压之间，并具有连接以接收电压（Vout1）的栅极。 差分放大器（AMP1）放大参考电压（Vref）和节点（F）的电压之间的差，并产生电压（Vout1）。 逆变器（I13）接收电压（Vout1）以产生高电压检测信号（VPPS）。

公开(公告)号：KR1020010105442A

公开(公告)日：2001-11-29

申请号：KR1020000024001

申请日：2000-05-04

Applicant: 삼성전자주식회사

Inventor： 이종언 ,  강상석 ,  임규남

IPC: G11C29/00

Abstract: 본 발명은 반도체 메모리 장치를 공개한다. 그 장치는 테스트시에 제1, 2내부 전압 선택신호들을 저장하기 위한 모드 설정 레지스터, 제1, 2내부 전압 선택신호들 각각에 응답하여 내부 부승압 전압과 내부 승압 전압을 선택하여 출력하기 위한 내부 전압 선택회로, 정상 동작시에 패드를 통하여 입출력되는 신호를 클램핑하고 테스트시에 내부 부승압 전압이 레벨 변동없이 패드를 통하여 출력될 수 있도록 하기 위한 패드 입/출력 레벨 제어회로, 및 상기 제1, 2내부 전압 선택신호들에 응답하여 정상 동작시에 패드를 통하여 전송되는 신호를 버퍼하여 출력하고, 테스트시에 디스에이블되는 입력 버퍼로 구성되어 있다. 따라서, 패키지 상태에서 내부 승압 및 부승압 전압을 측정할 수 있으므로 반도체 메모리 장치의 신뢰성이 향상될 수 있다.

公开(公告)号：KR1020000041361A

公开(公告)日：2000-07-15

申请号：KR1019980057220

申请日：1998-12-22

Applicant: 삼성전자주식회사

Inventor： 임규남 ,  차기원

IPC: H03K17/00

Abstract: PURPOSE: An internal power supply voltage generator is provided to have a rapid recovery time and a large driving capacity by realizing comparison circuits having MOS transistors of different channel rates. CONSTITUTION: An internal power supply voltage generator comprises a first comparison circuit(100), a second comparison circuit(200) and an output drive circuit(300). The first comparison circuit(100) compares an internal power supply voltage(IVCC) on an output terminal(400) with a reference voltage(Vref) to output a first comparison signal(COM1) as a comparison result. The second comparison circuit(200) compares the internal power supply voltage(IVCC) with the reference voltage(Vref) to output a second comparison signal(COM2) as a comparison result. The output driving circuit(300) is connected between an external power supply voltage and the output terminal(400), and drives the output terminal(400) according to the second comparison signal(COM2). The MOS transistors(110,120,130,140,150) of the first comparison circuit(100) have more large channel rates than those of the second comparison circuit(200).

Abstract translation: 目的：通过实现具有不同通道速率的MOS晶体管的比较电路，提供内部电源电压发生器以具有快速恢复时间和大的驱动能力。 构成：内部电源电压发生器包括第一比较电路（100），第二比较电路（200）和输出驱动电路（300）。 第一比较电路（100）将输出端子（400）上的内部电源电压（IVCC）与参考电压（Vref）进行比较，以输出第一比较信号（COM1）作为比较结果。 第二比较电路（200）将内部电源电压（IVCC）与参考电压（Vref）进行比较，以输出第二比较信号（COM2）作为比较结果。 输出驱动电路（300）连接在外部电源电压与输出端子（400）之间，根据第二比较信号（COM2）驱动输出端子（400）。 第一比较电路（100）的MOS晶体管（110,120,130,140,​​150）具有比第二比较电路（200）更多的信道速率。