公开(公告)号：KR1020050039236A

公开(公告)日：2005-04-29

申请号：KR1020030074666

申请日：2003-10-24

Applicant: 삼성전자주식회사

Inventor： 임규남

IPC: G11C11/40

Abstract: 동기식 반도체 메모리 장치에서 라스 액티브 레이턴시 기능을 수행하는 회로가 개시된다. 라스 액티브 레이턴시 기능 수행 회로는 동기회로와 파이프라인을 구비한다. 동기 회로는 라스 뱅크 액티브 커맨드를 생성하는 제어 신호들 및 라스 뱅크 액티브 커맨드에 대응되는 어드레스 신호를 내부 클락 신호에 동기시켜 전송한다. 파이프라인은 동기 회로를 통해 전송되는 제어 신호들과 어드레스 신호를 소정의 지연 시간만큼 지연하여 지연 제어 신호들과 지연 어드레스 신호를 발생한다. 동기 회로를 통해 전송되는 제어 신호들과 상기 파이프라인을 통해 발생되는 지연 제어 신호들의 논리 조합 및 지연 어드레스 신호에 의해 상기 라스 뱅크 액티브 커맨드에 대응되는 동작이 수행된다. 라스 액티브 레이턴시 기능 수행 회로는 리플레쉬 타임을 유지하면서 커맨드와 어드레스를 전송하는 버스의 사용 효율을 향상시킬 있다.

公开(公告)号：KR100452333B1

公开(公告)日：2004-10-12

申请号：KR1020020063789

申请日：2002-10-18

Applicant: 삼성전자주식회사

Inventor： 임규남

IPC: G11C5/14

CPC classification number: H03K17/223

Abstract: A power up signal generator includes a signal converter for converting an applied external source voltage to a voltage applied at a trigger node when the external source voltage rises to a first threshold, and a current source for flowing a reference current from the trigger node. A first inverter connected to the trigger node outputs a low level signal when the trigger node voltage reaches a second threshold. A second inverter outputs a power up signal after receiving the low level signal from the first inverter. The signal converter may include a PMOS transistor configuration, such that the trip voltage of the power up signal generator is dependent only on a single MOSFET transistor threshold voltage.

Abstract translation: 加电信号发生器包括信号转换器和电流源，该信号转换器用于在外部源电压上升到第一阈值时将施加的外部源电压转换为施加在触发节点处的电压，该电流源用于从触发节点流动参考电流。 当触发节点电压达到第二阈值时，连接到触发节点的第一反相器输出低电平信号。 第二个反相器在接收到来自第一个反相器的低电平信号后输出一个上电信号。 信号转换器可以包括PMOS晶体管配置，使得通电信号发生器的触发电压仅取决于单个MOSFET晶体管阈值电压。

公开(公告)号：KR1020030040726A

公开(公告)日：2003-05-23

申请号：KR1020010071144

申请日：2001-11-15

Applicant: 삼성전자주식회사

Inventor： 임규남 ,  유제환 ,  강영구 ,  심재윤

IPC: G11C7/12

CPC classification number: G11C7/065 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/2281

Abstract: PURPOSE: A semiconductor memory device is provided to be capable of easily controlling a bit line sensing operation without increasing a layout area. CONSTITUTION: A cell bit line precharge circuit(40) precharges a cell bit line pair(BLcell,BLBcell) by a voltage lower than the first voltage in response to a cell bit line precharge control signal(BLPRE). An SA(Sense Amplifier) bit line precharge circuit(44) precharges an SA bit line pair(BLsa,BLBsa) by the first voltage in response to an SA bit line precharge control signal(SAPRE). A charge transfer circuit(42,50) transfers charges between the cell bit line pair and the SA bit line pair in response to a control signal. The first sense amplifier circuit(46) amplifies a voltage of the SA bit line pair by the first voltage. The second sense amplifier circuit(48) amplifies a voltage of the SA bit line pair by the second voltage in response to an SA enable signal.

Abstract translation: 目的：提供半导体存储器件，以便能够容易地控制位线感测操作而不增加布局面积。 构成：单元位线预充电电路（40）响应于单元位线预充电控制信号（BLPRE），将单元位线对（BLcell，BLBcell）预充电低于第一电压的电压。 SA（感测放大器）位线预充电电路（44）响应于SA位线预充电控制信号（SAPRE），将SA位线对（BLsa，BLBsa）预充电第一电压。 电荷转移电路（42,50）响应于控制信号在单元位线对和SA位线对之间传送电荷。 第一读出放大器电路（46）将SA位线对的电压放大第一电压。 第二读出放大器电路（48）响应于SA使能信号，通过第二电压放大SA位线对的电压。

公开(公告)号：KR1020030037096A

公开(公告)日：2003-05-12

申请号：KR1020010068197

申请日：2001-11-02

Applicant: 삼성전자주식회사

Inventor： 임규남

IPC: G11C5/14

CPC classification number: G05F1/465

Abstract: PURPOSE: A circuit for generating an internal voltage is provided to control accurately a level of the internal voltage when an overshooting phenomenon is generated from the internal voltage. CONSTITUTION: A discharge current circuit(30) including the first and the second NMOS transistors(N4,N5) and a variable resistance(R1) is installed between a node(B) and ground voltage. The first NMOS transistor(N4) of the discharge current circuit(30) includes a drain connected with the node(B) and a gate. The second NMOS transistor(N5) includes a drain connected with the node(B), a source connected with the ground voltage, and a gate connected with a source of the first NMOS transistor(N4). The variable resistance(R1) is connected between the gate of the second NMOS transistor(N5) and the ground voltage.

Abstract translation: 目的：提供产生内部电压的电路，用于当从内部电压产生过冲现象时精确控制内部电压的电平。 构成：包括第一和第二NMOS晶体管（N4，N5）和可变电阻（R1）的放电电流电路（30）安装在节点（B）和接地电压之间。 放电电流电路（30）的第一NMOS晶体管（N4）包括与节点（B）连接的漏极和栅极。 第二NMOS晶体管（N5）包括与节点（B）连接的漏极，与地电压连接的源极和与第一NMOS晶体管（N4）的源极连接的栅极。 可变电阻（R1）连接在第二NMOS晶体管（N5）的栅极和接地电压之间。

公开(公告)号：KR100383267B1

公开(公告)日：2003-05-09

申请号：KR1020010009340

申请日：2001-02-23

Applicant: 삼성전자주식회사

Inventor： 임규남

IPC: G11C7/06

CPC classification number: G11C16/26

Abstract: A device according to the invention includes memory cells and a current sense amplifier. It also includes a feedback circuit to adjust a gain of the current sense amplifier. The gain is adjusted depending on relative delays of data stored in different ones of the memory cells to be read on the current sense amplifier.

Abstract translation: 根据本发明的器件包括存储器单元和电流感测放大器。 它还包括一个反馈电路来调整电流检测放大器的增益。 根据存储在要在电流感测放大器上读取的不同存储器单元中的数据的相对延迟来调整增益。

公开(公告)号：KR100366616B1

公开(公告)日：2003-01-09

申请号：KR1020000007522

申请日：2000-02-17

Applicant: 삼성전자주식회사

Inventor： 임규남

IPC: H03K19/0185

CPC classification number: H04L25/0292 ,  H03K19/01707 ,  H03K19/018528

Abstract: An input buffer circuit simultaneously supports a low voltage interface and a general low voltage transistor-transistor logic (LVTTL) interface and operates at high speed. In the input buffer circuit, a self bias voltage generated by a self biased differential amplification circuit is used not only for tracking a common mode input voltage in the differential amplification circuit but also for controlling the current of a current source and/or sink that controls the current used in the differential amplification circuit. Accordingly, the self bias voltage remains at a substantially uniform level. Therefore, the entire transconductance gain gm of the differential amplification circuit is substantially uniform regardless of the change in a reference voltage input to the differential amplification circuit. As a result, a low voltage interface characteristic is improved. The input buffer circuit can further include a swing width control circuit that responds to an inverted signal generated from the output signal of the differential amplification circuit and prevents the voltage swing of the output signal from becoming excessively large. This reduces skew and thus improves the operating speed of the input buffer.

Abstract translation: 输入缓冲电路同时支持低电压接口和通用低电压晶体管 - 晶体管逻辑（LVTTL）接口，并以高速运行。 在输入缓冲电路中，由自偏置差分放大电路产生的自偏置电压不仅用于跟踪差分放大电路中的共模输入电压，而且用于控制控制电流源和/或接收器的电流 在差分放大电路中使用的电流。 因此，自偏压保持在基本均匀的水平。 因此，不管输入到差分放大电路的参考电压的变化如何，差分放大电路的整个跨导增益gm基本均匀。 结果，低电压接口特性得到改善。 输入缓冲电路还可以包括摆幅控制电路，该摆幅控制电路响应于从差分放大电路的输出信号产生的反相信号并防止输出信号的电压摆幅变得过大。 这减少了偏斜，从而提高了输入缓冲器的运行速度。

公开(公告)号：KR100363327B1

公开(公告)日：2002-11-30

申请号：KR1020000014798

申请日：2000-03-23

Applicant: 삼성전자주식회사

Inventor： 임규남 ,  강상석

IPC: H01L27/02

Abstract: 여기에 개시되는 퓨즈 회로는 제 1 및 제 2 노드들에 각각 연결된 퓨즈 소자들과, 상기 퓨즈 소자들을 통해 흐르는 전류들의 차를 감지하는 감지 회로 및, 감지 회로는 그렇게 감지된 전류차에 따라 상기 제 1 및 제 2 노드들의 전압들을 설정하며, 상기 제 1 및 제 2 노드들의 전압들을 레일-레일 전압들로 각각 증폭하는 증폭 회로를 포함한다. 이러한 구성에 의하면, 퓨즈 소자들의 저항차를 전류차로 감지함으로써, 상기 노드들 각각의 용량성 기생 로딩의 크기에 관계없이 퓨즈 소자의 프로그램 유무를 정확하게 감지할 수 있다.

公开(公告)号：KR1020020072041A

公开(公告)日：2002-09-14

申请号：KR1020010012001

申请日：2001-03-08

Applicant: 삼성전자주식회사

Inventor： 임규남

IPC: G05F3/26

CPC classification number: G05F3/247 ,  G05F3/245 ,  Y10S323/907

Abstract: PURPOSE: A reference voltage generating circuit is provided to improve the credibility of a semiconductor memory device by generating a reference voltage which is independent of the increase of power voltage and increases depending on the temperature rise. CONSTITUTION: A bias current generating unit(20) is connected between a power source voltage and a ground voltage and generates a bias current that is increased according to the rising of temperature. A current generating unit is connected between a reference voltage generating terminal and the ground voltage and generates a reference voltage which is independent of the increase of power source voltage and increases depending on the temperature rise. The bias current generating unit(20) includes a starting circuit for generating a starting voltage and a bias current generating circuit for generating the bias current in response to the starting voltage.

Abstract translation: 目的：提供参考电压发生电路，通过产生与电源电压的增加无关的参考电压来提高半导体存储器件的可信度，并且根据温度升高而增加。 构成：偏置电流产生单元（20）连接在电源电压和接地电压之间，并产生根据温度升高而增加的偏置电流。 电流产生单元连接在参考电压产生端子和接地电压之间，并且产生与电源电压的增加无关的参考电压，并且根据温度升高而增加。 偏置电流产生单元（20）包括用于产生起始电压的起动电路和用于响应起动电压产生偏置电流的偏置电流产生电路。

公开(公告)号：KR1020000076683A

公开(公告)日：2000-12-26

申请号：KR1020000007522

申请日：2000-02-17

Applicant: 삼성전자주식회사

Inventor： 임규남

IPC: H03K19/0185

CPC classification number: H04L25/0292 ,  H03K19/01707 ,  H03K19/018528

Abstract: PURPOSE: A high-speed input buffer circuit is provided to satisfy a low-voltage interface and a low-voltage transistor-transistor logic interface at the same time. CONSTITUTION: A high-speed input buffer circuit comprises a differential amplifier(41) which supplies an internal self bias signal to an internal node(O1) and an output signal to an output node(O2) on the basis of a voltage difference between a reference voltage(VREF) and an input signal(IN). In order to maintain a voltage level of the self bias signal from the internal node(O1), a current adjusting circuit(43) supplies current to the differential amplifier and sinks current from the amplifier, in response to the self bias signal. A swing amplitude controller(45) prevents a swing amplitude of the output signal from the differential amplifier from being increased excessively in response to an inverted version of an output signal of the output node(O2).

Abstract translation: 目的：提供高速输入缓冲电路，以同时满足低压接口和低压晶体管晶体管逻辑接口。 构成：高速输入缓冲电路包括差分放大器（41），该差分放大器（41）基于内部节点（O1）和输出节点（O2）之间的电压差来向内部节点（O1）提供内部自偏置信号，并将输出信号提供给输出节点 参考电压（VREF）和输入信号（IN）。 为了保持来自内部节点（O1）的自偏置信号的电压电平，电流调节电路（43）响应于自偏置信号，向差分放大器提供电流并且从放大器吸收电流。 摆动振幅控制器（45）防止来自差分放大器的输出信号的摆幅振幅响应于输出节点（O 2）的输出信号的反转版本而过分增加。

公开(公告)号：KR100439024B1

公开(公告)日：2004-07-03

申请号：KR1020010012001

申请日：2001-03-08

Applicant: 삼성전자주식회사

Inventor： 임규남

IPC: G05F3/26

CPC classification number: G05F3/247 ,  G05F3/245 ,  Y10S323/907

Abstract: A reference voltage generating circuit of the present invention includes a start-up circuit connected between a power supply voltage and a ground voltage for generating a start-up voltage, a bias current generating circuit connected between the power supply voltage and the ground voltage for generating a bias current in response to the start-up voltage, the bias current increasing in response to an increase in temperature, a current generator connected between the power supply voltage and a reference voltage generating terminal for generating a mirrored current of the bias current, and a load connected between the reference voltage generating terminal and the ground voltage for generating a reference voltage that increases in response to any increase in temperature regardless of variations in the level of the power supply voltage. Accordingly, the level of reference voltage generated increases in response to increases in temperature regardless of variations in the level of the power supply voltage.

Abstract translation: 本发明的参考电压产生电路包括连接在电源电压和接地电压之间用于产生启动电压的启动电路，连接在电源电压和地电压之间的偏置电流产生电路，用于产生 响应于启动电压的偏置电流，偏置电流响应于温度的增加而增加;电流发生器，连接在电源电压和用于产生偏置电流的镜像电流的参考电压产生端子之间;以及 负载连接在参考电压产生端和地电压之间，用于产生参考电压，该参考电压响应于温度的任何增加而增加，而与电源电压的电平的变化无关。 因此，无论电源电压的电平如何变化，所产生的参考电压的电平响应于温度的增加而增加。