公开(公告)号：KR1020080104724A

公开(公告)日：2008-12-03

申请号：KR1020070051896

申请日：2007-05-29

Applicant: 삼성전자주식회사 ,  한국과학기술원

Inventor： 정성윤 ,  윤상보 ,  권영훈 ,  황성수 ,  이종호 ,  박현철 ,  김현국 ,  전기환

IPC: H04B7/08 ,  H04B7/04

CPC classification number: H04L25/0206 ,  H04L1/02 ,  H04B7/0413 ,  H04B7/08 ,  H04L1/0048

Abstract: A method for detecting signals based on QR-decomposition in a MIMO(Multiple Input Multiple Output) wireless communication system is provided to detect signals by antenna with low calculation complexity and to perform a QRD-M detection which has low calculation complexity. An RF(Radio Frequency) processing unit(202) converts a signal received through plural receiving antennas into a baseband signal, and a channel estimation unit(204) estimates channel information by antenna by using the signal processed by RF processor. A signal detector(206) receives the channel information from the channel estimation unit, selects symbol candidates which has Euclidean distance squared value lower than or same as reference value, and detects N number of transmission signals.

Abstract translation: 提供了一种用于在MIMO（多输入多输出）无线通信系统中基于QR分解来检测信号的方法，以低计算复杂度的天线检测信号，并执行具有低计算复杂度的QRD-M检测。 RF（射频）处理单元将通过多个接收天线接收的信号转换为基带信号，信道估计单元204使用由RF处理器处理的信号通过天线估计信道信息。 信号检测器（206）从信道估计单元接收信道信息，选择具有低于或等于参考值的欧氏距离平方值的符号候选，并检测N个发送信号。

公开(公告)号：KR100458288B1

公开(公告)日：2004-11-26

申请号：KR1020020005325

申请日：2002-01-30

Applicant: 한국과학기술원

Inventor： 이종호

IPC: H01L27/092 ,  B82Y40/00

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: PURPOSE: A dual gate FinFET device and a fabricating method thereof are provided to reduce fabricating cost and parasitic resistance by using a bulk wafer and forming an epitaxial layer on a source/drain. CONSTITUTION: A dual gate FinFET device includes a bulk silicon substrate(2b), a Fin active region(4), the second oxide layer(10), a gate oxide layer, the first oxide layer(6), a gate(16), a source/drain, a contact region, and a metal layer. The Fin active region is formed on the center portion of an upper portion of the bulk silicon substrate. The second oxide layer is formed on the surface of the bulk silicon substrate. The gate oxide layer is formed at both sidewalls of the Fin region of the second oxide layer. The first oxide layer is formed on an upper surface of the Fin active region. The gate is formed on the first and the second oxide layers. The source/drain is formed at both sides of the Fin active region except for an overlapped part between the gate and the Fin active region. The contact region and the metal layer are formed on the contact part of the source, the drain, and the gate.

Abstract translation: 目的：提供双栅极FinFET器件及其制造方法，以通过使用体晶片并在源极/漏极上形成外延层来降低制造成本和寄生电阻。 一种双栅FinFET器件，包括体硅衬底（2b），鳍有源区（4），第二氧化层（10），栅氧化层，第一氧化层（6），栅极（16） ，源极/漏极，接触区域和金属层。 Fin有源区形成在体硅衬底的上部的中心部分上。 第二氧化物层形成在体硅衬底的表面上。 栅极氧化物层形成在第二氧化物层的Fin区域的两个侧壁处。 第一氧化物层形成在Fin有源区的上表面上。 栅极形成在第一和第二氧化物层上。 源极/漏极形成在Fin有源区的两侧，除了栅极和Fin有源区之间的重叠部分之外。 接触区域和金属层形成在源极，漏极和栅极的接触部分上。