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公开(公告)号：KR1020120071880A
公开(公告)日：2012-07-03
申请号：KR1020100133606
申请日：2010-12-23
Applicant: 한국전자통신연구원
CPC classification number: H04L9/0637 , H04L2209/80 , H04W4/80 , H04W12/02
Abstract: PURPOSE: An RFID security reader is provided to operate a security engine at high speed by integrating a security engine to a modem of an RFID security reader. CONSTITUTION: A processor module(110) processes a security protocol and configures transmission data to an RFID(Radio Frequency ID) security tag. An encoding module(1221) encodes the transmission data. A decoding module(1222) decodes reception data which is received from the RFID security tag. A modem(120) processes the encoded data and processes the reception data.
Abstract translation: 目的：通过将安全引擎集成到RFID安全读取器的调制解调器，提供RFID安全读取器来高速运行安全引擎。 构成：处理器模块（110）处理安全协议并将传输数据配置到RFID（射频ID）安全标签。 编码模块（1221）对发送数据进行编码。 解码模块（1222）解码从RFID安全标签接收的接收数据。 调制解调器（120）处理编码数据并处理接收数据。
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公开(公告)号：KR1020110126074A
公开(公告)日：2011-11-22
申请号：KR1020110045159
申请日：2011-05-13
Applicant: 한국전자통신연구원
CPC classification number: H04L9/3273 , G06F21/445 , H04L2209/805 , H04Q2213/095
Abstract: PURPOSE: An RFID tag capable of supporting a normal mode and a security mode, interrogator, and operation method thereof are provided to offer various application services by supporting the function of a RFID tag and a security. CONSTITUTION: An operation mode determination unit(1200) determines a current operation mode. An operation state transition unit(1220) moves an operation state based on the current operation mode. When the current operation mode is determined to a security mode, the operation mode determination unit transmits PC(Protocol Control) information, a XPC_W2 parameter, a XPC_W1 parameter, and tag identification information to an interrogator. The operation mode determination unit includes a security channel forming unit.
Abstract translation: 目的：提供能够支持正常模式的RFID标签和安全模式，询问器及其操作方法，以通过支持RFID标签和安全性的功能来提供各种应用服务。 构成：操作模式确定单元（1200）确定当前操作模式。 操作状态转移单元（1220）基于当前操作模式移动操作状态。 当当前操作模式被确定为安全模式时，操作模式确定单元向询问器发送PC（协议控制）信息，XPC_W2参数，XPC_W1参数和标签识别信息。 操作模式确定单元包括安全通道形成单元。
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公开(公告)号：KR1020110024916A
公开(公告)日：2011-03-09
申请号：KR1020090083103
申请日：2009-09-03
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A location tracking apparatus, and a method and an apparatus for a location tracking service using the same are provided to track a location of a tag even though only one tag is recognized. CONSTITUTION: A GPS receiving unit(300) receives a GPS signal from a GPS satellite to generate self location information. A memory(310) stores unique ID information. A processor unit(320) generates the first transmission message frame using the self location information and unique ID information and generates the second transmission message frame using only the unique ID information.
Abstract translation: 目的：提供一种位置跟踪装置，以及使用其的位置跟踪服务的方法和装置，用于跟踪标签的位置，即使仅识别一个标签。 构成：GPS接收单元（300）从GPS卫星接收GPS信号以产生自身位置信息。 存储器（310）存储唯一的ID信息。 处理器单元（320）使用自身位置信息和唯一ID信息生成第一传输消息帧，并且仅使用唯一ID信息生成第二传输消息帧。
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公开(公告)号：KR100963416B1
公开(公告)日：2010-06-15
申请号：KR1020080086299
申请日：2008-09-02
Applicant: 한국전자통신연구원
Abstract: 보안 태그를 이용한 물품 유통 관리 장치 및 방법을 개시한다. 물품 유통 관리 방법은 물품에 부착된 보안 태그로부터 물품의 보안키를 리딩하는 단계와, 리딩한 보안키를 보안 서버로 전달하는 단계와, 전달된 보안키를 이용하여 암호화한 제1 인증정보를 보안 서버로부터 수신하는 단계와, 보안키를 이용하여 암호화한 제2 인증정보를 보안 태그로부터 수신하는 단계와, 제1 인증정보 및 제2 인증정보를 이용하여 보안 태그의 복제 여부를 판단하는 단계를 포함한다.
보안 태그, 복제, RFID-
公开(公告)号：KR1020100059567A
公开(公告)日：2010-06-04
申请号：KR1020080118382
申请日：2008-11-26
Applicant: 한국전자통신연구원
IPC: G01S5/06
Abstract: PURPOSE: A locating system and a signal receiver for the system are provided to accurately calculate the location of an object by correcting the signal detection time error between two devices. CONSTITUTION: A communications signal receiving device detects a synchronous signal for a communications signal and a time synchronization. The communications signal receiving device obtains a detection time interval and synchronous signal identifying information. A position calculation unit calculates the time detection error of the communications signal. A position determination device calculates the location of the object. A synchronous signal detector(30) detects the synchronous signal and synchronous signal identifying information. The communications signal detection unit(32) detects the communications signal.
Abstract translation: 目的：提供系统的定位系统和信号接收器，以通过校正两个设备之间的信号检测时间误差来精确计算对象的位置。 构成：通信信号接收装置检测通信信号的同步信号和时间同步。 通信信号接收装置获取检测时间间隔和同步信号识别信息。 位置计算单元计算通信信号的时间检测误差。 位置确定装置计算物体的位置。 同步信号检测器（30）检测同步信号和同步信号识别信息。 通信信号检测单元（32）检测通信信号。
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Patent Agency Ranking
公开(公告)号：KR100564769B1
公开(公告)日：2006-03-27
申请号：KR1020040009630
申请日：2004-02-13
Applicant: 한국전자통신연구원
IPC: H04L12/28
Abstract: 본 발명은 통신망을 통해 인터넷 서비스를 제공하고 동시에 다채널 방송 서비스를 제공하기 위한 멀티캐스트 라우터 및 이더넷 스위치에 관한 것으로, 특히 기존의 이더넷 기반의 네트워크에서 별도의 방송용 선로를 이용하지 않고 단일 회선으로 다채널 방송 서비스와 데이터 통신 서비스를 수용하여 방송 데이터와 통신 데이터의 융합 서비스를 제공하는 멀티캐스트 라우터 및 이더넷 스위치에 관한 것이다.
본 발명이 개시하는 방송 스트림 제공을 위한 멀티캐스트 라우터는 백본에서 입력되는 데이터에서 방송 스트림만을 검출하며, 백본 라인 인터페이스 보드에 구비된 방송 채널 검출기; 상기 스트림을 가입자 라인 인터페이스 보드에 broadcasting 하는 방송 분배 스위치; 및 상기 스위치로부터 상기 스트림을 분배받아 가입자가 요구한 방송 채널에 해당하는 방송 스트림만을 선택하여 상기 가입자에게 전송하며, 상기 가입자 라인 인터페이스 보드에 구비된 방송 채널 선택기를 포함하여 비방송 스트림과 방송 스트림을 분리하여 처리함으로써 본 발명의 목적 및 기술적 과제를 달성한다.-
公开(公告)号：KR100433637B1
公开(公告)日：2004-05-31
申请号：KR1020020032332
申请日：2002-06-10
Applicant: 한국전자통신연구원
IPC: H04L12/02
Abstract: PURPOSE: A router system interface device is provided to easily compose a line interface device because it is unnecessary to use a separate PCI(Peripheral Component Interconnect) bridge by using a processor having an interface function as a line processor. CONSTITUTION: A network processor(402) analyzes a received packet, and forwards the packet. A line processor(403) communicates with the network processor(402) by an embedded PCI function, and provides routing information to the network processor(402). A physical layer matching unit(401) connects with a certain external communication device, transmits and receives a signal with the communication device according to a certain protocol, and provides the received signal to the network processor(402) or the line processor(403). A switch interface unit(409) connects the network processor(402) with the line processor(403) through a back-plane. A device control matching function unit(410) initializes the network processor(402) and the line processor(403).
Abstract translation: 目的：提供路由器系统接口设备以便于组成线路接口设备，因为通过使用具有接口功能的处理器作为线路处理器，不需要使用单独的PCI（外围组件互连）桥接器。 构成：网络处理器（402）分析接收的分组，并转发该分组。 线路处理器（403）通过嵌入式PCI功能与网络处理器（402）通信，并向网络处理器（402）提供路由信息。 物理层匹配单元（401）与某个外部通信设备连接，根据特定协议与通信设备发送和接收信号，并将接收到的信号提供给网络处理器（402）或线路处理器（403） 。 交换机接口单元（409）通过背板将网络处理器（402）与线路处理器（403）相连接。 设备控制匹配功能单元（410）初始化网络处理器（402）和线路处理器（403）。
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48.发明公开패킷 처리 엔진과 메인 프로세서간에 고속 블록 데이터전송을 수행하는 네트워크 시스템 및 그것의 ＤＭＡ운영방법 失效用于执行分组处理引擎和主处理器之间的高速块数据传输的网络系统及其DMA的操作方法
公开(公告)号：KR1020030082253A
公开(公告)日：2003-10-22
申请号：KR1020020020904
申请日：2002-04-17
Applicant: 한국전자통신연구원
IPC: H04L12/771 , G06F13/28
CPC classification number: G06F13/28 , G06F13/1605
Abstract: PURPOSE: A network system for performing a high-speed block data transmission between a packet processing engine and a main processor, and a method for operating a DMA(Direct Memory Access) thereof are provided to reduce a DMA management function of the main processor and a processing time according to data transmission by setting a control state of a DMA engine in the DMA engine. CONSTITUTION: A processor processing buffer(220) stores packets to be processed in a CPU(110). A packet processing engine(240) forwards a packet inputted from a link in a wired speed, and generates a DMA request signal when the inputted packet is the packet to be processed in the CPU(110). A DMA engine(250) answers to the DMA request signal, monitors a residual quantity state of the processor processing buffer(220), and generates a control signal and an address necessary for a DMA operation.
Abstract translation: 目的：提供一种用于在分组处理引擎和主处理器之间执行高速块数据传输的网络系统，以及用于操作DMA（直接存储器访问）的方法，以减少主处理器的DMA管理功能， 通过在DMA引擎中设置DMA引擎的控制状态来进行数据传输的处理时间。 构成：处理器处理缓冲器（220）将要处理的分组存储在CPU（110）中。 分组处理引擎（240）以有线速度转发从链路输入的分组，并且当所输入的分组是要在CPU（110）中处理的分组时，生成DMA请求信号。 DMA引擎（250）应答DMA请求信号，监视处理器处理缓冲器（220）的剩余数量状态，并产生DMA操作所需的控制信号和地址。
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公开(公告)号：KR1020020053956A
公开(公告)日：2002-07-06
申请号：KR1020000081962
申请日：2000-12-26
Applicant: 한국전자통신연구원
IPC: G06F13/00
Abstract: PURPOSE: A processor board duplication system, and duplicated data reading and writing method is provided to arrange a FIFO(First Input First Output) memory logic at an active side board and a FIFO memory at a standby side board for duplicating data process between the two boards so that it can enhance a reliability and an availability of an overall system. CONSTITUTION: The system comprises an active side board(401) and a standby side board(410). The active side board(401) includes the first FIFO controller(403), the first processor(402), a buffer 1(404), the first FIFO, and a shared bus(405). The standby side board(410) includes the second processor(408), the second FIFO controller(407), the second FIFO(406), a buffer 2. The first FIFO controller(403) detects states(/FF2, /HF2) of the second FIFO(406). If the data can be transmitted as a result of the detection, the first processor(402) reads the data from a main memory, and stores the data at the second FIFO(406) via the shared bus(405). At this time, the active side board uses the data in a burst node in the case that the duplicated data fills in less than half of the FIFO memory when the first processor(402) checks the /HF signal. In the case that the duplicated data fills in more than half of the FIFO memory, the first processor(402) periodically reads the /FF signal, and writes the duplicated data by 1 byte. The second processor(408) enables the second FIFO controller(407) to check if duplicated data exists at the second FIFO(406). The data of the second FIFO(406), if it exists, is copied at the main memory of the standby side board(410). The second processor(408) periodically reads the /EF signal. The standby board reads the data in a burst node by using the /HF signal as an interrupt in the case that the duplicated data fills in more than half of the FIFO memory. In the case that the duplicated data fills in less than half of the FIFO memory, the CPU of the standby side board periodically reads the /EF signal, and reads the duplicated data.
Abstract translation: 目的：提供处理器板复制系统，并提供复制数据读写方法，以在主动侧板上设置FIFO（第一输入第一输出）存储器逻辑和备用侧板上的FIFO存储器，以复制两者之间的数据处理 板可以提高整体系统的可靠性和可用性。 构成：该系统包括主动侧板（401）和备用侧板（410）。 主动侧板（401）包括第一FIFO控制器（403），第一处理器（402），缓冲器1（404），第一FIFO和共享总线（405）。 备用侧板（410）包括第二处理器（408），第二FIFO控制器（407），第二FIFO（406），缓冲器2.第一FIFO控制器（403）检测状态（/ FF2，/ HF2） 的第二FIFO（406）。 如果作为检测的结果可以发送数据，则第一处理器（402）从主存储器读取数据，并且经由共享总线（405）将数据存储在第二FIFO（406）。 此时，当第一处理器（402）检查/ HF信号时，当复制数据填充少于FIFO存储器的一半时，主动侧板使用突发节点中的数据。 在复制的数据填充超过一半的FIFO存储器的情况下，第一处理器（402）周期性地读取/ FF信号，并将复制的数据写入1字节。 第二处理器（408）使得第二FIFO控制器（407）能够检查在第二FIFO（406）是否存在复制的数据。 第二FIFO（406）的数据（如果存在）被复制在备用侧板（410）的主存储器处。 第二处理器（408）周期性地读取/ EF信号。 在复制数据填充超过一半的FIFO存储器的情况下，备用板通过使用/ HF信号作为中断来读取突发节点中的数据。 在复制数据填满少于一半FIFO存储器的情况下，待机侧板的CPU周期性地读取/ EF信号，并读取重复的数据。
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公开(公告)号：KR1020170113861A
公开(公告)日：2017-10-13
申请号：KR1020160036891
申请日：2016-03-28
Applicant: 한국전자통신연구원
IPC: G01C19/56 , G01V3/08 , G08C17/02 , G06F3/0346
Abstract: 본발명은 IMU 모듈의제어장치및 그방법에관한것으로써, 본발명의일면에따른관성센서제어장치는, 하나이상의관성센서(IMU: Inertial Measurement Unit)를포함하는센서부; 상기센서부에의해측정된센서데이터를단말기또는측정장치로송신하는통신부; 및상기센서부의측정주기를상기센서부가장착된보행자의운동량에따라변경시키는제어부를포함하는것을특징으로한다.
Abstract translation: 本发明涉及IMU模块的控制装置和方法，其中根据本发明的一个方面的惯性传感器控制装置包括：传感器单元，其包括至少一个惯性测量单元（IMU） 通信单元，用于将由传感器单元测量的传感器数据传输到终端或测量装置; 以及控制单元，用于根据配备有传感器单元的行人的移动量来改变传感器单元的测量周期。
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