公开(公告)号：JPS5488726A

公开(公告)日：1979-07-14

申请号：JP15685877

申请日：1977-12-26

Applicant: FUJITSU LTD

Inventor： SUZUKI YOUICHI ,  HANADA AKIO ,  MITA TERUYOSHI ,  HOSHI FUMIO ,  SATOU MASAO

IPC: G06F3/02

Abstract: PURPOSE:To prevent the pick up of the switch address in erroneous form, by picking up the switch address information, through the countermeasures against chattering and bouncing of switches and mistouching and double touch. CONSTITUTION:The address information turned on or off is picked up by scanning the matrix switch 1 placed in matrix shape. In this case, the repetitive scanning circuit repetitively scanning the matrix switch 1 is provided and also, the address information pick up 6 set according to turning on or off of the switch detected at first during one scanning is provided with at least multi-pressing down FF. Further, on the condition that the synchronism taking the switch depression FF only at set state is continued for the number of times predetermined, the address information of the switch in ON or OFF state is picked up. Thus, the countermeasures against chaterring of switches etc. can prevent the switch address information in erroneous form from being picked up.

公开(公告)号：JPS60118932A

公开(公告)日：1985-06-26

申请号：JP22604283

申请日：1983-11-30

Applicant: FUJITSU LTD

Inventor： KABEMOTO AKIRA ,  BABA YASUO ,  SATOU MASAO

IPC: G06F9/38 ,  G06F9/32 ,  G06F12/08

Abstract: PURPOSE:To decrease the amount of components by utilizing an operation processing section to compare a write address and a next instruction fetch address, thereby eliminating the need for a check section exclusive for the comparison. CONSTITUTION:A detecting section 23 detects the relation of 0

公开(公告)号：JPS6045848A

公开(公告)日：1985-03-12

申请号：JP15281883

申请日：1983-08-22

Applicant: FUJITSU LTD

Inventor： SATOU MASAO

IPC: G06F7/00 ,  G06F7/57 ,  G06F11/20

Abstract: PURPOSE:To obtain a correct result with a small number of cycles by providing an input/output information switching means and a logical arithmetic control means, and switching a logical arithmetic unit to another nondefective unit when an error generated in said unit. CONSTITUTION:When an error occurs to a logical arithmetic unit ALU21, an error detecting circuit ALUCK51 for logical arithmetic unit transmits an error signal ALUERB0 to a logical arithmetic control part ALCONT1. Then the ALCONT1 executes a recovery cycle. That is, the ALCONT1 controls multiplexers MPX43, 44 and 45 and a carry CRY62 to select a terminal B and a COB1 and uses an ALU22 in place of the ALU21 to execute the operation of B0. In such a way, an arithmetic unit having an error is switched to another nondefective unit. Thus a correct result is obtained with a small number of cycles.

公开(公告)号：JPS5958556A

公开(公告)日：1984-04-04

申请号：JP16891982

申请日：1982-09-28

Applicant: Fujitsu Ltd

Inventor： SATOU MASAO

IPC: G06F11/10 ,  G06F12/14

CPC classification number: G06F11/10

Abstract: PURPOSE:To permit a data processor to send out error information to a storage protection address and to inverts the parity of data on the bus and reports that to peripheral equipments when detecting an error during cycle steal operation. CONSTITUTION:When the error detecting circuit 14 in the data processor 3 detects an error during cycle steal operation, an encoding circuit 15 codes the error information. The encoded information ''F'' is sent out to the storage protection address bus 17 and also inputted to a parity inverting circuit 16. The parity inverting circuit 16 generates wrong parity to the data ''F'' and sends it out to the storage protection address bus 17. The data ''F'' on the address bus 17 is inputted to a peripheral equipment 2 through a peripheral equipment 1. The peripheral equipment 2 detects a parity error by a parity error detecting circuit 8 to know the occurrence of the error during the cycle steal operation. The kind of the error is discriminated by decoding the data ''F'' by a decoding circuit 10.

Abstract translation: 目的：允许数据处理器将错误信息发送到存储保护地址，并在总线窃取操作期间检测到错误时将总线上的数据的奇偶校验转换为外围设备的报告。 构成：当数据处理器3中的错误检测电路14在循环窃取操作期间检测到错误时，编码电路15对错误信息进行编码。 编码信息“F”被发送到存储保护地址总线17并且还输入到奇偶校验反相电路16.奇偶校验反相电路16对数据“F”产生错误的奇偶校验，并将其发送到 存储保护地址总线17.地址总线17上的数据“F”通过外围设备1输入到外围设备2.外围设备2通过奇偶校验错误检测电路8检测奇偶校验错误，以知道发生 的循环窃取操作中的错误。 通过解码电路10对数据“F”进行解码来辨别错误的种类。

公开(公告)号：JPS595356A

公开(公告)日：1984-01-12

申请号：JP11443482

申请日：1982-06-30

Applicant: Fujitsu Ltd

Inventor： SATOU MASAO ,  ICHIJIYOU AKIHIRO

IPC: G06F9/34 ,  G06F11/16

CPC classification number: G06F11/16

Abstract: PURPOSE:To continue processing without stopping hardware, by reading out and operating again a data of a part where an error occurs, from a register which generates no error, even if an error exists in data which is read out of two general-purpose registers. CONSTITUTION:Two general registers GRA, GRB which store the same data are controlled by a register controlling circuit GRC. For instance, an address R1 and R2 are read out of the GRA and the GRB, and when no error is detected ED, the operation ALU is executed through selecting circuits MPA-B and work regiters WRA-B, and the result is stored in the address R1 of the GRA-B. Supposing an error is detected ED in R1, a signal SEL-GRB is outputted, the address R1 is read out of the GRb, and the MPA selects the R1 from a BUS-B and sets it to the WRA. Subsequently, this R1 and the R2 set to the WRB before are operated ALU, and are stored in the address R1 of the GRA and the GRB. In this way, even if an error occurs, the processing is not stopped, and high-speed properties and reliability are maintained.

Abstract translation: 目的：即使从两个通用寄存器读出的数据中存在错误，也可以从不产生错误的寄存器中读取并重新生成发生错误的部分的数据，从而继续处理硬件。 。 构成：存储相同数据的两个通用寄存器GRA，GRB由寄存器控制电路GRC控制。 例如，从GRA和GRB中读出地址R1和R2，当没有检测到错误时，通过选择电路MPA-B和工作寄存器WRA-B执行操作ALU，结果存储在 GRA-B的地址R1。 假设在R1中检测到ED，则输出信号SEL-GRB，从GRb读出地址R1，MPA从BUS-B中选择R1并将其设置为WRA。 随后，R1和R2之前设置的WRB被操作ALU，并存储在GRA和GRB的地址R1中。 以这种方式，即使发生错误，也不停止处理，并且保持高速性能和可靠性。

公开(公告)号：JPS56127258A

公开(公告)日：1981-10-05

申请号：JP2993380

申请日：1980-03-10

Applicant: FUJITSU LTD

Inventor： HOSHI FUMIO ,  SATOU MASAO

IPC: G06F12/06

Abstract: PURPOSE:To ensure an automatic operation of the packing capacity that varies when the number of memory supporters is varied, by generating the disposition signal when the memory supporter is mounted accurately at the prescribed position and then generating the packing capacity indication signal by a combination of the disposition signals to then decode the indication signal. CONSTITUTION:A main storage comprises the memory supporters m-1, m-2-m-8 containing the memory elements. When the supporter m-1 is mounted accurately, the disposition signal showing the accurate mounting of m-1 is applied to the terminal T1. When the supporter m-2 is mounted accurately, the disposition signal showing this is applied to the terminal T2. The same procedure is carried out thereafter. Then the capacity indication signal generating circuit 7 generates the capacity indication signal by a combination of the disposition signals for decoding of the capacity indication signal. Thus an automatic operation 1 is possible for the packing capacity that varies when the number of the supporters m-1-m-8 is varied.