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    Multidrop communication control system
    41.
    发明专利
    Multidrop communication control system 失效
    多媒体通信控制系统

    公开(公告)号：JPS58198940A

    公开(公告)日：1983-11-19

    申请号：JP8263482

    申请日：1982-05-17

    Applicant: Fujitsu Ltd

    Inventor： KITANO YOSHIHIRO ,  MITA TERUYOSHI

    IPC: H04L12/52

    CPC classification number: H04L12/525

    Abstract: PURPOSE:To obtain an economical and highly-flexible system without increasing the hardware amount of circuit opposite parts connected in large quantity to station nodes, by bringing data transfer and control between a master and a slave station by a monitoring device. CONSTITUTION:When a time slot counter 12 indicates (m), an address (m) of a frame buffer memory address circuit 13 is accessed to read previously stored time slot numbers (i) and (j). Then, data on a time slot number (m) stored in a data buffer register 7 is stored in the addresses 1 and (j) of a frame buffer memory 8. On the other hand, the data written in the frame buffer memory 8 is read out successively as the time slot counter 12 goes up, and sent out to a transmission line. The circuit opposite parts in station nodes monitor only time slots addressed to own station to receive the time slots (i and j in this case) addressed to own station.

    Abstract translation: 目的：通过监控设备在主站和从站之间进行数据传输和控制，获得经济，高度灵活的系统，不会增加大量连接到站点节点的相对电路的硬件数量。 构成：当时隙计数器12指示（m）时，访问帧缓冲存储器地址电路13的地址（m）以读取先前存储的时隙号（i）和（j）。 然后，存储在数据缓冲寄存器7中的时隙号（m）的数据被存储在帧缓冲存储器8的地址1和（j）中。另一方面，写入帧缓冲存储器8的数据是 随着时隙计数器12上升，连续读出，并发送到传输线。 站点节点的相对部分的电路仅监视寻址到本站的时隙，以接收寻址到本站的时隙（在这种情况下为i和j）。

    FSK SIGNAL DEMODULATING SYSTEM
    44.
    发明专利
    FSK SIGNAL DEMODULATING SYSTEM 失效

    公开(公告)号：JPS57210750A

    公开(公告)日：1982-12-24

    申请号：JP9483581

    申请日：1981-06-19

    Applicant: FUJITSU LTD

    Inventor： SAKATA TAKAO ,  TSUTSUI HIDEKAZU ,  MITA TERUYOSHI ,  UMIGAMI SHIGEYUKI

    IPC: H04L27/156 ,  H04L27/14

    Abstract: PURPOSE:To demodulate a data signal without distortion from a PCM-coded FSK signal, through the decision of an accurate zero cross point, by interpolating a sampling value before and after the zero cross point. CONSTITUTION:A PCM code is serial-parallel-converted with a signal frequency- dividing a clock CK by 1/8 and inputted to registers REG1 and REG2 sequentially. When a polarity inversion detecting circuit DET compares signals from both the registors and detects zero crossing, a load signal is provided for a count circuit CT via an AND gate and delay circuits DEL1 and DEL2. On the other hand, a memory M generates an interpolation value(n) based on both signals of the REG1 and REG2 and presets the count circuit CT to this value. The circuit CT counts the clock CK and outputs K. A subtraction circuit SUB operates K-n and a discrimination circuit JU outputs a zero cross point signal based on the result of the SUB. An output signal with timing adjustments is measured for a time between zero cross points and is taken as demodulation signal for the FSK signal.

    DATA HIGHWAY SYSTEM
    45.
    发明专利
    DATA HIGHWAY SYSTEM 失效

    公开(公告)号：JPS5691557A

    公开(公告)日：1981-07-24

    申请号：JP16902179

    申请日：1979-12-25

    Applicant: FUJITSU LTD

    Inventor： KITANO YOSHIHIRO ,  MITA TERUYOSHI

    IPC: G06F13/00 ,  H04L12/42

    Abstract: PURPOSE:To make it possible to detect addresses of all nodes at a time by sending back characteristic addresses from respective nodes in response to general polling information, including an indication command for address setting switch content transmission, from a loop controller. CONSTITUTION:The address setting switch content transmission indication command received from transmission line 20 is decoded by decoding circuit GP0 and stored in FF6. A go-ahead pattern arriving thereafter is detected by detecting circuit GAP and stored in FF8. Consequently, address setting switch content transmission timing is sent from gate G1 and the contents of address setting switch 16 are sent from gate G4 and OR gate G6 to transmission line 20. Thus, addresses set to all nodes can be detected at a time by the loop controller through single polling from the loop controller.

    DATA HIGHWAY SYSTEM
    46.
    发明专利
    DATA HIGHWAY SYSTEM 失效

    公开(公告)号：JPS5623057A

    公开(公告)日：1981-03-04

    申请号：JP9861279

    申请日：1979-08-03

    Applicant: FUJITSU LTD

    Inventor： KITANO YOSHIHIRO ,  SUZUKI YOUICHI ,  MITA TERUYOSHI

    Abstract: PURPOSE:To decrease the time for retransmission and to reduce the load to the system, by retransmitting the same packet from the memory in the control unit after a given time without sending the end signal to the subsystem, when the content of response from the reception control unit is busy. CONSTITUTION:The data buffer 3 of a plurality of communication control units 1 is connected in right with the transmission line through the reception section 2 and the transmission section 4 to perform the detection of vacant packet and arrival packet with the common control section 5, and the packet buffer memory 7 of the channel section 8 stores the data for transmission and reception and perform the giving and receiving of packet with the subsystem. When the packet fed from the transmission section 4 returns after circulating the transmission line, the content of response is interpreted with the decoder of the channel control section 6, and if the busy is discriminated, the timer in the control section 6 is started and transmission request signal is fed to the memory 7 when a given time is elapsed after start and the same packet in the memory 7 is again fed on the transmission line via the buffer 3.

    PACKET SWITCHING TYPE DATA HIGHWAY SYSTEM
    47.
    发明专利
    PACKET SWITCHING TYPE DATA HIGHWAY SYSTEM 失效

    公开(公告)号：JPS55138946A

    公开(公告)日：1980-10-30

    申请号：JP4746679

    申请日：1979-04-18

    Applicant: FUJITSU LTD

    Inventor： SUZUKI YOUICHI ,  KITANO YOSHIHIRO ,  MITA TERUYOSHI

    IPC: H04L12/437

    Abstract: PURPOSE:To obtain a data system which can be utilized for preventive maintenance, etc. for failure by extracting the control information such as communication amount, busy probability, etc. in the supervisory device, and has connected the supervisory device and several communication devices in a loop. CONSTITUTION:The supervisory device 1 is connected to several communication devices which are not shown in Fig. through the data highway 3, and a communication frame between the communication devices passes at all times. As for the shift registers 4-6 in the supervisory device 1, a called subscriber address A1, a calling station address A2 an a control field C in the communication frame have been set respectively and at that moment the contents are transmitted to the comparison coincidence circuits 13-15 of the pattern detection parts 7-9. The coincidence circuits 13-15 make the counters 16-18 step forward and make them extracted control data, when the instruction patterns of the registers 10-12 in which the information to be extracted that is decided beforehand is stored, and the information patterns from the registers 4-6 have been matched.

    CONTROL SYSTEM FOR POWER SUPPLY
    48.
    发明专利
    CONTROL SYSTEM FOR POWER SUPPLY 失效

    公开(公告)号：JPS55107361A

    公开(公告)日：1980-08-18

    申请号：JP1411879

    申请日：1979-02-09

    Applicant: FUJITSU LTD

    Inventor： SUZUKI YOUICHI ,  MITA TERUYOSHI

    IPC: H04L12/42

    Abstract: PURPOSE:To enable to apply the power supply of each communication unit automatically, by detecting the leading of the power feeding voltage when the voltage is first fed to the feeding line. CONSTITUTION:When the power supply switch of the communication unit N1 is twined on, the power feeding voltage at the power feeding line 2 is increased and the power supply feeding voltage detection relay of other communication units is operated. Since the charging current flows to the capacitor C with the closing of the contact rl1, the power supply relay RL3 is energized to close the power supply contact S. Thus, AC voltage is fed to the power supply 5. Accordingly, DC voltage is fed to the relay unit 3 from the power supply 5. In this case, the output voltage detection relay RL4 is operated, allowing to feed power to the relay unit 3 from the power feeding line 2.

    SECTIONING AND INFORMING SYSTEM FOR ADDRESS INFORMATION
    49.
    发明专利
    SECTIONING AND INFORMING SYSTEM FOR ADDRESS INFORMATION 失效

    公开(公告)号：JPS54119848A

    公开(公告)日：1979-09-18

    申请号：JP2703178

    申请日：1978-03-09

    Applicant: FUJITSU LTD

    Inventor： SUZUKI YOUICHI ,  KUGIMIYA SETSUO ,  MITA TERUYOSHI ,  NAKAMURA HIROSHI ,  HANADA AKIO

    IPC: G06F13/16

    Abstract: PURPOSE:To enable to inform the address information from the transfer control unit to the memory unit, by sectioning the address information to be informed into a plurality of address groups and transferring the address information to the memory unit via the address bus one by one group. CONSTITUTION:When cycle steal request is taken place, the request is informed to the memory unit 2 via the control line 10. Further, the address information stored in the address information register 7 is sectioned into a plurality of address group and the address information is transferred to the memory unit 2 via the address information line 9 one by one group. The control in which any of the gates 11-1 to 11- 3 is opened and how many times the address group is fed, is performed with the address information selection and judgement circuit 8. As a result, the address information having the number of bits greater than the bus width of the address bus can be transferred to the memory unit.

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