公开(公告)号：JPS62257237A

公开(公告)日：1987-11-09

申请号：JP10012686

申请日：1986-04-30

Applicant: FUJITSU LTD

Inventor： SUZUKI HIDEO ,  NOJIMA SATOSHI ,  NAKAMURA OSAMU

IPC: H04L7/00 ,  H04L1/00 ,  H04L1/18 ,  H04L7/08 ,  H04L25/02 ,  H04L25/49

Abstract: PURPOSE:To improve the reliability without lowering the transmission efficiency by changing the initial pattern of a scramble pattern generator when a transmission error is detected and the data is sent again. CONSTITUTION:A retransmission device 3 detects a transmission error and sends the data by the reply from a receiving side and timeout supervision, In applying retransmission, the scramble pattern generator 1 forms a scramble pattern based on the initial pattern other than the initial pattern for the preceding scramble pattern, the probability to recover the transmission error generated by the band condition scramble pattern is improved by applying the scramble. In repeating the retransmission, since the initial pattern is changed by the initial pattern change device 2 at every occasion, the probability is improved further thereby improving the reliability. The initial pattern is sent at the head of the transmission frame for the descrmabling at the reception side.

公开(公告)号：JPS61240739A

公开(公告)日：1986-10-27

申请号：JP8187085

申请日：1985-04-17

Applicant: FUJITSU LTD

Inventor： NAKAHARA YASUHIRO ,  MITA TERUYOSHI ,  KITANO YOSHIHIRO ,  NEGISHI HITOSHI ,  NAKAMURA OSAMU ,  INOUE YUKINORI

Abstract: PURPOSE:To shorten the check time of a list sequence, and to improve the real time property of a system by providing a function for detecting quickly a list sequence error of a station node for forming an annular data transmission line. CONSTITUTION:In a data highway system which has been constituted of a network monitoring device NSP 1, a highway monitoring device SV 2, and station nodes SN 1-5, etc., a function for detecting quickly a list sequence error of the SNs 1-5 is provided. That is to say, a control part FLEO 44 for generating and releasing a spurious transmission line fault, an FLE 148, etc. are provided, and a start for generating the spurious transmission line fault to the SV 2 or the SNs 1-5 is executed. As a result, the spurious transmission line fault of a LINE '0' system is propagated to SN3, SN2, SN4 and SN5 through SN1 of the '0' system, and when the fault is detected by the SN2, it is informed to the NSP 1. Also, even in case of a LINE '1' system, the processing is executed in the same way. By such a processing, a list sequence can be checked quickly, the releasing work time is shortened, and the real time property of the system can be improved.

公开(公告)号：JPS61221951A

公开(公告)日：1986-10-02

申请号：JP6440085

申请日：1985-03-28

Applicant: FUJITSU LTD

Inventor： INOUE YUKINORI ,  KITANO YOSHIHIRO ,  NAKAMURA OSAMU

IPC: G06F13/00 ,  G06F13/20 ,  G06F13/36

Abstract: PURPOSE:To detect quickly a double selection phenomenon of a common bus and to prevent the effect of the double selection from expanding in a wide range, by connecting successively the data transfer devices at both the selecting side and the side to be selected via detecting signal lines and then connecting these lines to a detection control part. CONSTITUTION:A data transfer device 20 at the selecting side and data transfer devices 21-1 and 21-2 at the side to be selected are connected successively via detecting signal lines 23-1-23-4. Thus a circular signal transmission line is formed. The signal lines 23-1 and 23-2 are connected to a detection control part 22, and the output side of the part 22 is connected to the signal lines 23-2 and 23-3 led to the following transfer devices. In the same way, the output side of the control part 22 of the final one of those transfer devices connected successively is connected to the line 23-4. Then the device 20 checks the signal of the line 23-4 at a proper time point after transmission of a selected address. Thus a double selection phenomenon can be detected.

公开(公告)号：JPS61150544A

公开(公告)日：1986-07-09

申请号：JP27601484

申请日：1984-12-25

Applicant: FUJITSU LTD

Inventor： NAKAMURA OSAMU ,  MITA TERUYOSHI ,  KITANO YOSHIHIRO ,  NAKAHARA YASUHIRO ,  NEGISHI HITOSHI

Abstract: PURPOSE:To improve the use efficiency of a time slot by executing data transmission to the other terminal from one terminal by loading data on an assigned time slot, and executing data transmission to one terminal from the other terminal by using an in-node data bus means, in case when point-to-point communication between each of a pair of terminals of plural terminals which have been connected to the same node. CONSTITUTION:In continuous time slots TSi, TSi+1, TSi and TSi+1 are assigned to a circuit corresponding part A and a circuit corresponding part B, respectively. When TSi comes to a buffer 9, the circuit corresponding part A raises a processing request status, a control part 13 allows a selector 14 to select an input 1 by a signal 1, and data (a transmitting data from the terminal B) of TSi in the buffer 9 is read into the circuit corresponding part A. When TSi+1 comes to the buffer 9, transmitting data from the circuit corresponding part A is read into the circuit corresponding part B, and also a signal 18 is controlled so that the contents of an input 2 are inputted to a P/S converter 11 by the next shift clock.

公开(公告)号：JPS6157146A

公开(公告)日：1986-03-24

申请号：JP17966184

申请日：1984-08-29

Applicant: Fujitsu Ltd

Inventor： KITANO YOSHIHIRO ,  MITA TERUYOSHI ,  INOUE YUKINORI ,  NAKAHARA YASUHIRO ,  NEGISHI HITOSHI ,  NAKAMURA OSAMU

Abstract: PURPOSE: To improve the utilizing efficiency of a time slot by setting a communication bus identification number to each communication controller, adding it to a control section in a time slot and transmitting the result.
CONSTITUTION: A transmission data generated by a data terminal device 74 is stored in a transmission buffer register circuit 72 via a level converting circuit 73, and when a prescribed amount of data is stored, a control section 70 detects an idle time slot. The control section 70 detecting the idle time slot writes a communication bus identification number and a USE bit and transmits a transmission data via a data transmission line 52. the time slot assigned to the own device reaches the communication controller at the reception side and it is coincident with the assigned communication bus identification number, the data of the time slot is written in a reception buffer register 71 to reset the USE bit and the data is transmitted to the terminal device 74.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：通过将通信总线识别号码设置给每个通信控制器来提高时隙的利用效率，将其添加到时隙中的控制部分并发送结果。 构成：由数据终端装置74生成的发送数据通过电平转换电路73存储在发送缓冲寄存器电路72中，并且当存储规定量的数据时，控制部70检测空闲时隙。 检测空闲时隙的控制部70写入通信总线识别号和USE位，并经由数据传输线52发送发送数据。分配给自身装置的时隙到达接收侧的通信控制器， 与分配的通信总线识别号一致，时隙的数据被写入接收缓冲器寄存器71以复位USE位，并且数据被发送到终端装置74。

公开(公告)号：JPS60170352A

公开(公告)日：1985-09-03

申请号：JP2537584

申请日：1984-02-14

Applicant: FUJITSU LTD

Inventor： MITA TERUYOSHI ,  SUZUKI YOUICHI ,  NAKAMURA OSAMU

IPC: H04L7/00 ,  H04L12/42

Abstract: PURPOSE:To eliminate the necessity of a high-grade phase regulating circuit so as to suppress the increase in the cost of a communication device, by installing a phase regulating circuit to each of plural communication devices commonly using an annular main line. CONSTITUTION:A phase regulating circuit 23 is provided in a communication device 21 and has a converting or invertedly converting phase regulating function. Another phase regulating circuit 24 is provided in another communication device 22 and has the same function as the regulating circuit 23 has. Then the regulating circuit 23 of the communication device 21 is set to a condition where phase regulation is inhibited, and the regulating circuit 24 of the communication device 22 is set to another circuit where phase regulation is controlled. Since the phase regulating function of the regulating circuit 23 is inhibited, a stable element timing signal can be supplied to a synchronizing MODEM5. Therefore, the necessity of a high-grade phase regulating circuit is eliminated and, as a result, the cost of the communication device can be prevented from increasing.

公开(公告)号：JPS6035643B2

公开(公告)日：1985-08-15

申请号：JP12501176

申请日：1976-10-20

Applicant: FUJITSU LTD

Inventor： NAKAMURA OSAMU ,  TSUKAMOTO MAKOTO ,  MIKI MASAJI

IPC: G02B6/28 ,  G02B27/10

公开(公告)号：JPS602253B2

公开(公告)日：1985-01-21

申请号：JP4147578

申请日：1978-04-07

Applicant: FUJITSU LTD

Inventor： NAKAMURA OSAMU ,  TATSUTA TAKASHI

IPC: C03B37/023 ,  G02B6/00

公开(公告)号：JPS59231950A

公开(公告)日：1984-12-26

申请号：JP10712483

申请日：1983-06-15

Applicant: FUJITSU LTD

Inventor： NAKAMURA OSAMU ,  MITA TERUYOSHI ,  KITANO YOSHIHIRO ,  NAKAHARA YASUHIRO ,  NEGISHI TSUTAE

IPC: H04L5/22 ,  H04L12/12 ,  H04L11/00 ,  H04J3/00

Abstract: PURPOSE:To eliminate the malfunction of a terminal device without proving a reception data buffer more than the required number of sets to a line correspondence section by eliminating a time slot remaining to a transmission line after the line correspondence section releases the time slot. CONSTITUTION:The line correspondence section 12 is provided corresponding to a common control section of a station node of a data highway and the correspondence section 12 is provided with a transmission buffer 20, a reception buffer 22, a register 24 and an address comparator 25. Further, an S/P converter 21, a P/S converter 23 and a timer 26 or the like are provided. When communication is finished by the correspondence section 12, a program is read by the OFF of a signal 31 for a line cut-off request from the terminal device so as to activate the buffer 22 and the converter 23. After the correspondence section 12 opens the time slot, the time slot remaining to the transmission line by the register 24, the address comparator 25 and the timer 26 or the like is eliminated, the number of the buffers 22 required for the correspondence section 12 is reudced, thereby preventing the malfunction of the terminal device.

公开(公告)号：JPS595761A

公开(公告)日：1984-01-12

申请号：JP11443582

申请日：1982-06-30

Applicant: Fujitsu Ltd

Inventor： NAKAMURA OSAMU ,  MITA TERUYOSHI

IPC: H04L12/43

CPC classification number: H04L12/43

Abstract: PURPOSE:To making a data transfer speed constant and to eliminate the need for frame monitoring, by providing a means of transmitting data from a slave station to a master station synchronously with the significance/insignificance flag of data set when the data is sent from the master station to the slave station. CONSTITUTION:The station 3 of the master station 6 while writing transmit data to a slave station in the data area of a time slot M writes ''1'' in an AV area and then transmits the data to a loop transmission line 1. On the other hand, stations 4 and 5 including slave stations 7 and 8 check on AV areas of time slots from the master station and set the contents of the time slot with ''1'' as significant data in an LS including the slave station. At this time, when there is data to be sent from the slave station to the master station, the transmit data is written in the data area of a time slot S and the AV area with ''1'' is sent out to the transmission line 1 as it is. The master station checks on the AV area of the time slot after one round and when it indicates ''1'', the data from the slave station is set in the LS as significant data.

Abstract translation: 目的：为了使数据传输速度恒定并且消除对帧监视的需要，通过提供一种将数据从从站发送到主站同时与数据集的有效/无意义标志同步发送的方法 主站到从站。 构成：在将时隙M的数据区域中的从站发送数据的时候，主站6的站3在AV区域中写入“1”，然后将数据发送到环路传输线路1上 另一方面，包括从站7和8的站4和5检查来自主站的时隙的AV区域，并将包含从站的LS中的“1”的时隙的内容设置为有效数据。 此时，当从从站发送数据到主站时，将发送数据写入时隙S的数据区域，将具有“1”的AV区域发送到发送 第1行。 主站在一轮后检查时隙的AV区域，当它指示“1”时，来自从站的数据被设置在LS中作为重要数据。