公开(公告)号：JPS62292042A

公开(公告)日：1987-12-18

申请号：JP13647386

申请日：1986-06-12

Applicant: FUJITSU LTD

Inventor： TOMINAGA SUSUMU ,  NOJIMA SATOSHI ,  SAKAKAWA KAZUO

Abstract: PURPOSE:To process a multicast packet at a high speed, by adding an address obtained from a table, on the multicast packet stored and accumulated temporarily at a feedback circuit, at the time of transmitting the multicast packet. CONSTITUTION:When the same data is multiple-addressed from a terminal equipment (a) to terminal equipments (b), (c), and (d), the equipment (b), and a node 3 are posted on the control table 14 of a node 2 as a transmission opposite. And at the time of arriving a packet at a reception circuit 11 from the equipment (a), a circuit 13 reads out a first transmission opposite, for example, the equipment (b) from the table 14, and adds it on the packet, then sends it to a transmission circuit 12. The circuit 12 sends it to the equipment (b), and also, holds the data part of it at a feedback circuit 15. Next, the circuit 13 reads out the node 3 that is a second transmission opposite, from the table 14, and generates a second transmission packet by adding the node 3 on the data held at the circuit 15, and transmits it from the circuit 12 to the node 3.

公开(公告)号：JPS62257237A

公开(公告)日：1987-11-09

申请号：JP10012686

申请日：1986-04-30

Applicant: FUJITSU LTD

Inventor： SUZUKI HIDEO ,  NOJIMA SATOSHI ,  NAKAMURA OSAMU

IPC: H04L7/00 ,  H04L1/00 ,  H04L1/18 ,  H04L7/08 ,  H04L25/02 ,  H04L25/49

Abstract: PURPOSE:To improve the reliability without lowering the transmission efficiency by changing the initial pattern of a scramble pattern generator when a transmission error is detected and the data is sent again. CONSTITUTION:A retransmission device 3 detects a transmission error and sends the data by the reply from a receiving side and timeout supervision, In applying retransmission, the scramble pattern generator 1 forms a scramble pattern based on the initial pattern other than the initial pattern for the preceding scramble pattern, the probability to recover the transmission error generated by the band condition scramble pattern is improved by applying the scramble. In repeating the retransmission, since the initial pattern is changed by the initial pattern change device 2 at every occasion, the probability is improved further thereby improving the reliability. The initial pattern is sent at the head of the transmission frame for the descrmabling at the reception side.

公开(公告)号：JPS62176239A

公开(公告)日：1987-08-03

申请号：JP1751786

申请日：1986-01-29

Applicant: FUJITSU LTD

Inventor： TOMINAGA SUSUMU ,  NOJIMA SATOSHI ,  HASEBE TAKAYUKI

Abstract: PURPOSE:To eliminate the effect of a measured communication line onto traffic by informing a signal representing the packet sending from the transmission side to the reception side through other line than the transmission line and allowing the reception side to measure the time until the arrival of packet after the signal is detected. CONSTITUTION:A packet transmission data bus 101 and a signal line 102 are provided between the transmission side and the reception side. A measuring packet sending signal representing the sending of a packet is sent to a signal line by a measuring packet sending signal generating means 103 at the transmission side. A packet transferred from a comparison means 104 at the reception side via the data bus 101 and the same packet received via a packet communication line are collated and a transmission delay time measuring means 105 measures the time from the detection of a measured packet sending signal till the coincidence of collation of the packets to measure the transmission delay of the packet.

公开(公告)号：JPS61171243A

公开(公告)日：1986-08-01

申请号：JP1216685

申请日：1985-01-25

Applicant: FUJITSU LTD

Inventor： TSUTSUI HIDEKAZU ,  NOJIMA SATOSHI ,  TOMINAGA SUSUMU

IPC: H04J3/17

Abstract: PURPOSE:To realize multiplication of a channel generated intermittently with a good channel utilizing efficiency by describing a time slot and channel assignment information of the next frame to a header having a fixed length having plural split time slots. CONSTITUTION:The frame consists of a frame synchronizing pattern 22, a header 20 and a time slot 21 and the frame header 21 has assignment information of the time slot of the next frame in itself. The time slot and the channel assignment information are written in the frame header. Time slot is assigned for the share of the number of time slots used in each channel at the transmission side and the next frame is transmitted. The frame header is checked at the reception side, a channel used for the next frame is recognized to obtain the relation of time slot assignment of the next frame together with the number of time slots used by each channel known in advance.

公开(公告)号：JPS58120349A

公开(公告)日：1983-07-18

申请号：JP385882

申请日：1982-01-13

Applicant: FUJITSU LTD

Inventor： ARITAKA TOKUHIRO ,  HASHIMOTO MASAMICHI ,  TAKEYAMA AKIRA ,  NOJIMA SATOSHI ,  TAZAKI TAKASHI

IPC: H04L25/40 ,  H04L5/16 ,  H04L7/00

Abstract: PURPOSE:To simplify the constitution and to make the synchronism easy, by detecting the start of a flag pattern of a transmission data at a secondary station and controlling the clock of the transmission circuit, in a loop synchronizing control system using a pair of transmission circuits in common. CONSTITUTION:A transmission request signal 15 from a transmission circuit 1 is high, then the start of flag pattern of the transmission data 12 is detected at an operation mode control circuit 3, a clock control signal 16 goes to high, a clock control circuit 2 is controlled with this signal and the clock signal is kept high. The circuit 3 receives a reception data 11 from the loop and detects a Goar head GA pattern, then the clock control signal 16 is made low and the operating mode is made to the transmission mode. Thus, the transmission data 12 is transmitted to the loop as the transmission data 13 from the circuit 1. Through the operation like this, the GA pattern of the reception data 11 is converted into a flag pattern like the transmission data 13.

公开(公告)号：JPS58107962A

公开(公告)日：1983-06-27

申请号：JP20784481

申请日：1981-12-22

Applicant: FUJITSU LTD

Inventor： NOJIMA SATOSHI ,  TAKEYAMA AKIRA ,  ARITAKA TOKUHIRO ,  TAZAKI TAKASHI

IPC: G06F9/46 ,  G06F9/48

Abstract: PURPOSE:To limit the queue waiting time and to average it without increasing a queue processing buffer, by determining the priority with predetermined evaluating function, and assigning the order of priority to a processor from the queue having the maximum evaluating value. CONSTITUTION:Every time a data of processing request is inputted to queue buffers 4-1-4-n in the order of priority, the data is counted with queue length counters 5-1-5-n, and the value and the priority value predetermined are inputted to evaluation function circuits 6-1-6-n and the result of evaluation is inputted to an order of priority determining section 8. Thus, the section 8 makes determination and outputs 1 to AND circuits 7-1-7-n corresponding to the queue buffer having the highest priority and assigns the result to a processor 10 via an OR circuit 9. In this case, the operation of subtraction of 1 from the counted value of the queue counter corresponding to the assigned queue buffer is repeated.

公开(公告)号：JPS57192151A

公开(公告)日：1982-11-26

申请号：JP7699981

申请日：1981-05-21

Applicant: FUJITSU LTD ,  NIPPON TELEGRAPH & TELEPHONE

Inventor： NOJIMA SATOSHI ,  SHINRAI TAKASHI ,  YATSUHOSHI AKIMASA ,  TAKAHASHI TATSUROU ,  AOYAMA TOMONORI ,  UEDA HIROMI

IPC: H04L29/02 ,  H04L12/801 ,  H04L12/911

Abstract: PURPOSE:To speed up the packet signal transmission and to increase the number of allocated subscribers per processor, by providing a buffer memory for each of reception and transmission section of a packet processor and making the data transmission of each packet at a DMA controller. CONSTITUTION:HDLC circuits 4 and 4' making rearrangement of packets corresponding to a subscriber are arranged and the circuits 4 and 4' are provided respectively with line memories 51 and 51' having functions as buffer memories. The memories 51 and 51' are connected with a memory 3, a processor 2 and a direct memory access controller DMAC1 via a bus line 6. Through the control of the DMACA1, the types and address of packets are discriminated at the memory 51 with the access from the processor 2 and the relayed packet is transmitted to the memory 51' with one time of DMA via a bus 9. Further, the packet required for the processing is transmitted to the memories 51 and 51' through the memory 3 on a bus 10 to speed up the transmission of packet signals.

公开(公告)号：JPH041543B2

公开(公告)日：1992-01-13

申请号：JP15048182

申请日：1982-08-30

Applicant: FUJITSU LTD

Inventor： TAKEYAMA AKIRA ,  TAZAKI TAKASHI ,  NOJIMA SATOSHI ,  ARITAKA TOKUHIRO ,  MITA TERUYOSHI

IPC: H04L12/437

公开(公告)号：JPH03270439A

公开(公告)日：1991-12-02

申请号：JP6815090

申请日：1990-03-20

Applicant: FUJITSU LTD

Inventor： NOJIMA SATOSHI ,  TOMINAGA SUSUMU

IPC: H04L12/827

Abstract: PURPOSE:To speedily cancel a crowded state such as congestion by controlling the crowded state of a route while controlling a route to be stored in a self- packet exchange node by each packet exchange node. CONSTITUTION:When the congestion or the like is generated in a certain packet exchanging node or in a transmission line housed in the node, the information is announced to the other packet exchange node as crowded state announcement. In such a case, a route discriminating means 104 retrieves the route included in the transmission line corresponding to the crowded state announcement 107 from a route storing means 101 and out of the retrieved routes, a route 108 to be housed in the self-packet exchange node. Only to the discriminated route 108, the control of the crowded state is executed by a route control means 105 based on the crowded state announcement 107. Thus, only the packet data of the route directed to the transmission line generating the congestion or the like is speedily regulated and the crowded state of the congestion is speedily canceled.

公开(公告)号：JPH0310542A

公开(公告)日：1991-01-18

申请号：JP14608189

申请日：1989-06-08

Applicant: FUJITSU LTD

Inventor： NOJIMA SATOSHI ,  YATSUHOSHI AKIMASA

IPC: H04L12/70 ,  H04L12/951

Abstract: PURPOSE:To shorten a voice packet composing time by using a packet composing means so as to use a sampled voice signal at the same sampling point of the same sampling clock on plural voice communication lines thereby forming a prescribed length of packet. CONSTITUTION:Voice signals of 20 channels are sampled simultaneously with an 8kHz sampling clock by using A/D converters 10, 11...12 and each 8-bit PCM signal of the 20 channels is stored in registers 13, 14...15 for each 125mus. Then a packet composing circuit 2 fetches the 8-bit PCM signal into the buffer memory 16 from the registers 13, 14...15 for a time of 125mus to latch the succeeding PCM signal in the registers 13, 14...15. Then the PCM signal fetched in the buffer memory 16 is used to compose the packet.