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公开(公告)号：JPH0448011B2
公开(公告)日：1992-08-05
申请号：JP2702985
申请日：1985-02-14
Applicant: FUJITSU LTD
Inventor： TSUTSUI HIDEKAZU , NOJIMA SATOSHI , HASHIMOTO MASAMICHI , TOMINAGA SUSUMU , SAKAKAWA KAZUO
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公开(公告)号：JPS62104243A
公开(公告)日：1987-05-14
申请号：JP24315185
申请日：1985-10-30
Applicant: FUJITSU LTD
Inventor： SAKAKAWA KAZUO , KANOCHI JUNICHI , HASHIMOTO MASAMICHI
Abstract: PURPOSE:To attain the real time processing of packet composition at each channel by generating a transmission header corresponding to a channel during communication, adding it to a data extracted from a buffer at each prescribed period to constitute a packet. CONSTITUTION:A processor 1 sets identification information (b) in an identification information memory 3 corresponding to a channel number ch=i set to a call to logical '1'. After a transmission header hi is stored in the transmission header memory 4, a control section 7 references the identification information memory 3 periodically and when a channel number ch=i in which the identification information (b) is set to logical '1' is detected, a header addition circuit 5 adds the transmission header hi extracted from the memory 4 to the data di extracted from a packet composition buffer 2 to compose a data packet pdi. Thus, the assembling load of the data packet is eliminated from the processor 1 and the data packet requesting the real time of voice is composed.
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公开(公告)号：JPS627228A
公开(公告)日：1987-01-14
申请号：JP14637285
申请日：1985-07-03
Applicant: FUJITSU LTD
Inventor： HASHIMOTO MASAMICHI
Abstract: PURPOSE:To avoid system-down at deterioration of a satellite line by avoiding transmission from a slave station so long as demand assignment control information received from both network systems I, II is not coincident. CONSTITUTION:A master station data burst DB0 is provided after a reference burst FRB of a TDMA frame. A master station I2 of a network I uses a reference burst FRB to send demand assignment control information to subsequent slave stations I31-I3n and also to a master station II2 of the network II at the same time. The master station II2 uses a master station data burst DB'0 to send the demand assignment information of the network I to slave stations II31-II3n of the network II. The slave stations II31-II3n send the received demand assignment information to slave stations I31-III3n respectively. The slave stations I31-I3n collate the demand assignment control information received from both the systems and apply changeover only when they are coincident.
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公开(公告)号：JPS61216545A
公开(公告)日：1986-09-26
申请号：JP2702985
申请日：1985-02-14
Applicant: FUJITSU LTD
Inventor： TSUTSUI HIDEKAZU , NOJIMA SATOSHI , HASHIMOTO MASAMICHI , TOMINAGA SUSUMU , SAKAKAWA KAZUO
Abstract: PURPOSE:To reduce the number of first in first out buffers and simplify circuit configuration by providing the third first in first out buffer only between multiplexed first bus and second bus, and increasing multiplicity of the first or second bus, and increasing multiplicity of the first or second first in first out buffer within allowable limit of the first and second buses. CONSTITUTION:Packets arrived from each incoming communication channel 101 are accumulated successively in each buffer 6. Each receiving and transferring circuit 11 poles the buffer 6 connected to corresponding bus 8 and extracts accumulated packets. Each receiving and transferring circuit 11 interprets transmission header of extracted packet, and identifies outgoing communication channel 102 to transfer, and selects a buffer 10 provided at intersection with a bus 9 to which a buffer 7 corresponding to the outgoing communication channel 102 of address of transfer, and accumulates after confirming that there is room for accumulation in the buffer 10. Similarly, each transmitting and transferring circuit 12 accumulates extracted packets in the buffer 7. Packets accumulated in each buffer 7 are extracted successively and sent out to the outgoing communication channel 102.
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公开(公告)号：JPS58123246A
公开(公告)日：1983-07-22
申请号：JP646682
申请日：1982-01-19
Applicant: FUJITSU LTD
Inventor： HASHIMOTO MASAMICHI , ARITAKA TOKUHIRO
IPC: H04B10/27 , H04B10/035 , H04B10/038 , H04B10/077 , H04B10/275 , H04J14/02 , H04L12/42
Abstract: PURPOSE:To obtain an optical communication system which uses a single ringlike transmission line controllable effectively in case of a fault by transmitting a signal by light having different wavelength, and using the wavelength conversion part of a prescribed node and constituting a loop-back transmission line. CONSTITUTION:In a normal state, looped signal transmission uses wavelength lambda1. In case of the occurrence of a fault, a monitor control station SV detects its position, sends indications of connection switching to the wavelength conversion part WLC, the actuation of the conversion part WLC, and transmission (loop-back constitution) in the arrival direction of lambda1 using wavelength lambda2 to nodes on both sides by utilizing a monitor control signal sent with the wavelength lambda1. Consequently, a large looped transmission line is formed by light signals sent in the opposite directions.
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Patent Agency Ranking
公开(公告)号：JPS5797252A
公开(公告)日：1982-06-16
申请号：JP17303680
申请日：1980-12-08
Applicant: FUJITSU LTD
Inventor： ARITAKA NORIHIRO , HASHIMOTO MASAMICHI
Abstract: PURPOSE:To collect detailed information on failures of monitored stations, by providing bits for detailed monitor control information in a plurality of monitor control bits in a data frame. CONSTITUTION:A monitor control station (hereinafter called a SV station) makes transfer instruction of detailed data to monitored stations (hereinafter called node stations), by using several frames to several tens of frames of a transfer bit 21 shown in Fig. A. Each node station makes transfer to the next station with a transmission/reception switching section 7 if the instruction data from the said SV station is not destined for the station itself. On the other hand, when the instruction data from the said SV station is destined for the station itself, a station control section 16 returns ruquired data corresponding to the instruction to the SV station. Thus, detailed monitor control information can be transmitted from the node stations to the SV station with the instruction from the SV station separately from polling monitor control information by using several frames to several tens of frames of transfer bit 21 in Fig. A.
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公开(公告)号：JPS56162559A
公开(公告)日：1981-12-14
申请号：JP6681880
申请日：1980-05-20
Applicant: FUJITSU LTD
Inventor： HASHIMOTO MASAMICHI , ARITAKA TOKUHIRO
Abstract: PURPOSE:To equalize the transmission speed of transmission to that of reception easily by selecting a start-stop synchronizing clock on the basis of read data by sending only one start bit from a transmission side and by reading the one bit at a reception side with a receiving clock having a high transmission speed. CONSTITUTION:Firstly, only one start bit is sent from a transmission side and this start bit is read by a start-stop synchronous receiving circuit 2 at a reception side. In this case, a clock CKn for receiving data having the highest transmission speed estimated in advance is used for the read and the read data is transferred to a microprocessor 5 via a bus 7. Then, the read data is judged by the processor 5 to discriminate its transmission speed and on the basis of the discrimination result, the selection of the clock of a clock selecting circuit 3 is controlled through an interface circuit 4 to equalize the transmission speed of transmission to that of reception easily.
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公开(公告)号：JPS5664541A
公开(公告)日：1981-06-01
申请号：JP14008079
申请日：1979-10-30
Applicant: FUJITSU LTD
Inventor： HASHIMOTO MASAMICHI , ARITAKA TOKUHIRO , TSURUMAKI SHINZOU
Abstract: PURPOSE:To realize assuredly the setting of the clock for a start-stop synchronous receiving circuit with a simple circuit constitution, by producing the data of 1-bit width at the transmission side and then measuring the time duration at the reception side respectively. CONSTITUTION:The input data having the time duration equivalent to the start bit is supplied through the transmission line 1 and in the form of the received data. This data is sampled through the sampling circuit 2, and the output of this sampling circuit 2 is supplied to the counter 3. Then the clock selection circuit 4 sets the input clock of the start-stop synchronous receiving circuit 5 in a correct way according to the value of the counter 3.
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公开(公告)号：JPS55102062A
公开(公告)日：1980-08-04
申请号：JP902179
申请日：1979-01-29
Applicant: FUJITSU LTD
Inventor： KAMEI SABUROU , KAMEO KIYOUJI , HASHIMOTO MASAMICHI
IPC: G06F11/30
Abstract: PURPOSE:To enable to avoid runaway by inhibiting the operation of controlled unit with control signal, through the inhibition of the output of enable signal when the output OFF is detected from the watchdog timer. CONSTITUTION:When the computer system 1 receives the control signal output instruction, the control signal A is outputted. In this case, the enable signal B and the pulse D from the watchdog timer are simultaneously outputted. The enable signal B is inputted to the two-stage shift register 2 and the pulse D is inputted to the two-stage shift register 2 and the detector 3. When the pulse D is normally outputted from the two-stage shift register 2, the enable signals C1-C2 are sequentially outputted. If program runaway is taken place due to some causes, the pulse D is not outputted. When the detector 3 detects it, the signal E is outputted to inhibit the output from the shift register 2. Accordingly, no controlled unit is operative even with the control signal instruction received.
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公开(公告)号：JPS6342530A
公开(公告)日：1988-02-23
申请号：JP18740786
申请日：1986-08-08
Applicant: FUJITSU LTD
Inventor： HASHIMOTO MASAMICHI
Abstract: PURPOSE:To prevent collision between data bursts even in case the demand assign instruction of a master station does not reach a slave station, by additionally distributing an addable excess time equally to inter-station guard times by the master station when the addable excess time is changed with extension/ reduction of the data burst length of some station. CONSTITUTION:When change and extension of the burst length are requested in a data burst DB1 of a station 3-1, an arrangement 1 of data bursts is changed to an arrangement 2, and the old data burst DB1 is to a new data burst DB1, 2 and a maximum extension width is 2Tc. The master station extends the data burst DB1 as shown by the arrangement 2 and equally divides a total sum 3Tc of the excess time in a frame by the number of data bursts to calculate a new excess time Tc' as shown by an arrangement 3 and adds this excess time to a guard time Tg and distributes lines to one data burst again for every one demand assign instruction. Thus, even if a difference is caused between adjacent sequences in map information related to lines, it has an influence on only data bursts of one station which assigns lines.
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