公开(公告)号：US20240068985A1

公开(公告)日：2024-02-29

申请号：US17821836

申请日：2022-08-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Laura J. Silverstein

IPC: G01N27/414 ,  B01L3/00 ,  G01N21/05

CPC classification number: G01N27/4145 ,  B01L3/502715 ,  G01N21/05 ,  B01L2300/047 ,  B01L2300/0636 ,  B01L2300/0645

Abstract: A structure includes a lab-on-chip (LOC) sensor and frontside port and cavity features for conveying a flowable sample (fluid or gas) to a sensing element of the sensor. The cavity is confined within middle of the line (MOL) dielectric layer(s). Alternatively, the cavity includes a lower section within MOL dielectric layer(s), an upper section within back end of the line (BEOL) dielectric layer(s) in the first metal (M1) level, a divider between the sections, and a duct linking the sections. Alternatively, the cavity includes a lower portion within MOL dielectric layer(s) and an upper portion continuous with the lower portion and within BEOL dielectric layer(s) in the M1 level. Optionally, the cavity is separated from the sensing element by an additional dielectric layer and/or at least partially lined with a dielectric liner. The port extends from the top of the BEOL dielectric layers down to the cavity.

公开(公告)号：US20230405582A1

公开(公告)日：2023-12-21

申请号：US17807896

申请日：2022-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bartlomiej J. Pawlak ,  Ramsey M. Hazbun ,  Siva P. Adusumilli ,  Mark D. Levy

IPC: B01L3/00 ,  G01N27/414

CPC classification number: B01L3/502715 ,  B01L2200/12 ,  G01N27/414 ,  B01L3/502707

Abstract: Disclosed is a semiconductor structure including a monocrystalline silicon layer having a first surface and a second surface opposite the first surface. A cavity extends into the first semiconductor layer at the second surface. The structure also includes a polycrystalline silicon layer adjacent to the second surface and extending over the cavity. At least one opening extends through the second semiconductor layer to the cavity.

公开(公告)号：US20230207639A1

公开(公告)日：2023-06-29

申请号：US18174052

申请日：2023-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768

CPC classification number: H01L29/401 ,  H01L29/7786 ,  H01L29/66462 ,  H01L29/41766 ,  H01L29/42316 ,  H01L21/76897 ,  H01L29/42376 ,  H01L29/4983

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US20230178449A1

公开(公告)日：2023-06-08

申请号：US17643023

申请日：2021-12-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Rajendran Krishnasamy ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H01L23/367 ,  H01L29/732 ,  H01L23/373 ,  H01L29/417

CPC classification number: H01L23/367 ,  H01L29/7325 ,  H01L23/3736 ,  H01L29/41708

Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.

公开(公告)号：US11588056B2

公开(公告)日：2023-02-21

申请号：US16992440

申请日：2020-08-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Jagar Singh

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: A structure includes a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer over the semiconductor substrate, and an SOI layer over the buried insulator layer. At least one polycrystalline active region fill shape is in the SOI layer. A polycrystalline isolation region may be in the semiconductor substrate under the buried insulator layer. The at least one polycrystalline active region fill shape is laterally aligned over the polycrystalline isolation region, where provided. Where provided, the polycrystalline isolation region may extend to different depths in the semiconductor substrate.

公开(公告)号：US20230034728A1

公开(公告)日：2023-02-02

申请号：US17389779

申请日：2021-07-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhong-Xiang He ,  Richard J. Rassel ,  Alvin J. Joseph ,  Ramsey M. Hazbun ,  Jeonghyun Hwang ,  Mark D. Levy

IPC: H01L21/768 ,  H01L23/48 ,  H01L29/778 ,  H01L29/66 ,  H01L21/8234

Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

公开(公告)号：US11322639B2

公开(公告)日：2022-05-03

申请号：US16844606

申请日：2020-04-09

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Vibhor Jain ,  Ramsey Hazbun ,  Pernell Dongmo ,  Cameron E. Luce ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L31/107 ,  H01L31/18 ,  H01L31/028 ,  H01L31/0376

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an avalanche photodiode and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom composed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material provided on the first semiconductor material; and a third semiconductor material provided on the photosensitive semiconductor material.

公开(公告)号：US11316064B2

公开(公告)日：2022-04-26

申请号：US16887375

申请日：2020-05-29

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Mark D. Levy ,  Vibhor Jain ,  Andre Sturm

IPC: H01L31/107 ,  H01L31/105 ,  H01L31/036 ,  H01L31/028 ,  H01L31/0312

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one fin including substrate material, the at least one fin including sidewalls and a top surface; a trench on opposing sides of the at least one fin; a first semiconductor material lining the sidewalls and the top surface of the at least one fin, and a bottom surface of the trench; a photosensitive semiconductor material on the first semiconductor material and at least partially filling the trench; and a third semiconductor material on the photosensitive semiconductor material.