公开(公告)号：US12205943B2

公开(公告)日：2025-01-21

申请号：US17890725

申请日：2022-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain F. Loiseau ,  Souvick Mitra ,  Rajendran Krishnasamy

IPC: H01L27/02 ,  H01L29/73 ,  H01L29/735 ,  H01L29/739

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.

公开(公告)号：US12170329B2

公开(公告)日：2024-12-17

申请号：US17692218

申请日：2022-03-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Vvss Satyasuresh Choppalli ,  Rajendran Krishnasamy

IPC: H01L29/78 ,  H01L21/3215 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

Abstract: According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

公开(公告)号：US12170313B2

公开(公告)日：2024-12-17

申请号：US18324637

申请日：2023-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L21/763 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

公开(公告)号：US20240266422A1

公开(公告)日：2024-08-08

申请号：US18166041

申请日：2023-02-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Satyasuresh Vvss Choppalli ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Anindya Nath

IPC: H01L29/745

CPC classification number: H01L29/7455

Abstract: Disclosed structures include a semiconductor controlled rectifier or bi-directional semiconductor controlled rectifier with a trigger voltage (Vtrig) that is tunable. Some structures include a semiconductor controlled rectifier with an Nwell and Pwell in a semiconductor layer, with a P-type diffusion region in the Nwell, and with an N-type diffusion region in the Pwell. Gate(s) on the well(s) are separated from the junction between the wells and from the diffusion regions. Other structures include a bidirectional semiconductor controlled rectifier with a Pwell between first and second Nwells in a semiconductor layer, with first P-type and N-type diffusion regions in the first Nwell, and with second P-type and N-type diffusion regions in the second Nwell. Gate(s) on the well(s) are separated from junctions between the Nwells and the Pwell and from any diffusion regions. In these structures, the gate(s) can be left floating or biased to tune Vtrig using gate leakage current.

公开(公告)号：US20240186429A1

公开(公告)日：2024-06-06

申请号：US18062201

申请日：2022-12-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli ,  Ramsey M. Hazbun

IPC: H01L31/0224 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/18

CPC classification number: H01L31/022408 ,  H01L31/03125 ,  H01L31/1037 ,  H01L31/1812

Abstract: A photodiode and a related method of manufacture are disclosed. The photodiode includes a transfer gate and a floating diffusion adjacent to the transfer gate. In addition, the photodiode includes an upper terminal; an intrinsic semiconductor region in contact with the upper terminal, the intrinsic semiconductor region in a trench in a substrate adjacent to the transfer gate; and a lower terminal in contact with the intrinsic semiconductor region. An insulator layer is along an entirety of a sidewall of the intrinsic semiconductor region and between the intrinsic semiconductor region and the transfer gate. A p-type well may also optionally be between the insulator layer and the transfer gate.

公开(公告)号：US11869941B2

公开(公告)日：2024-01-09

申请号：US17679166

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sarah A. McTaggart ,  Rajendran Krishnasamy ,  Qizhi Liu

IPC: H01L21/265 ,  H01L29/732 ,  H01L29/737 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0817 ,  H01L21/26586 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

Abstract: Disclosed are a structure including a transistor and a method of forming the structure. The transistor includes an emitter region with first and second emitter portions. The first emitter portion extends through a dielectric layer. The second emitter portion is on the first emitter portion and the top of the dielectric layer. An additional dielectric layer covers the top of the second emitter portion. The second emitter portion and the dielectric and additional dielectric layers are wider than the first emitter portion. At least a section of the second emitter portion is narrower than the dielectric and additional dielectric layers, thereby creating cavities positioned vertically between edge portions of the dielectric and additional dielectric layers and positioned laterally adjacent to the second emitter portion. The cavities are filled with dielectric material or dielectric material blocks the side openings to the cavities creating pockets of air, of gas or under vacuum.

公开(公告)号：US20230395590A1

公开(公告)日：2023-12-07

申请号：US17805697

申请日：2022-06-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR.

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: An integrated circuit (IC) structure with a conductive pathway through resistive semiconductor material, e.g., for bipolar transistors, is provided. The IC structure may include a resistive semiconductor material having a first end coupled to a first doped semiconductor material. The first doped semiconductor material has a first doping type. A doped well may be coupled to a second end of the resistive semiconductor material. The doped well has a second doping type opposite the first doping type. A second doped semiconductor material is coupled to the doped well and has the first doping type. The resistive semiconductor material is within a conductive pathway from the first doped semiconductor material to the second doped semiconductor material.

公开(公告)号：US20230387333A1

公开(公告)日：2023-11-30

申请号：US17664741

申请日：2022-05-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Ramsey Hazbun

IPC: H01L31/0216 ,  H01L31/18 ,  H01L31/105

CPC classification number: H01L31/0216 ,  H01L31/1804 ,  H01L31/105 ,  H01L31/022408

Abstract: A photodetector structure includes a first semiconductor material layer on a first portion of a doped well in a substrate. The photodetector structure includes a second semiconductor layer over the first semiconductor layer. The first and second semiconductor material layers may include an undoped semiconductor material. The photodetector structure includes an insulative collar laterally surrounding the first and second semiconductor material layers. The insulative collar may include a varying horizontal thickness. The photodetector structure includes a doped semiconductor material having an opposite doping polarity relative to the doped well, and positioned over the second semiconductor material layer and the insulating collar.

公开(公告)号：US20230317869A1

公开(公告)日：2023-10-05

申请号：US17709181

申请日：2022-03-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli ,  Ramsey Hazbun ,  Steven M. Shank

IPC: H01L31/105 ,  H01L31/0224 ,  H01L31/18

CPC classification number: H01L31/105 ,  H01L31/022408 ,  H01L31/1812

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and methods of manufacture. The structure includes: a top terminal; an intrinsic material in contact with the top terminal; and a bottom terminal in contact with the intrinsic material, the bottom terminal including a P semiconductor material and a fully depleted N semiconductor material.

公开(公告)号：US11777043B1

公开(公告)日：2023-10-03

申请号：US17807887

申请日：2022-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey M. Hazbun ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Siva P. Adusumilli

IPC: H01L31/0352

CPC classification number: H01L31/035281

Abstract: A substrate is formed to include a substrate base and a substrate extension. A photodiode contacts the substrate base. The substrate extension is adjacent the photodiode. An additional device contacts the substrate extension. A sidewall spacer contacts the photodiode and the substrate extension. The additional device includes conductive elements within the substrate extension adjacent the sidewall spacer.