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公开(公告)号:US12278269B2
公开(公告)日:2025-04-15
申请号:US17852966
申请日:2022-06-29
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Uppili S. Raghunathan , Vibhor Jain , Qizhi Liu , Yves T. Ngu , Ajay Raman , Rajendran Krishnasamy , Alvin J. Joseph
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.
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公开(公告)号:US12230673B2
公开(公告)日:2025-02-18
申请号:US17708561
申请日:2022-03-30
Applicant: GlobalFoundries U.S. Inc.
Inventor: Michel Abou-Khalil , Steven M. Shank , Aaron Vallett , Sarah McTaggart , Rajendran Krishnasamy
IPC: H01L29/06 , H01L29/10 , H01L29/423
Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.
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公开(公告)号:US12191300B2
公开(公告)日:2025-01-07
申请号:US17662921
申请日:2022-05-11
Applicant: GlobalFoundries U.S. Inc.
Inventor: Robert J. Gauthier, Jr. , Rajendran Krishnasamy , Anupam Dutta , Anindya Nath , Xiangxiang Lu , Satyasuresh Vvss Choppalli , Lin Lin
IPC: H01L27/02
Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.
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公开(公告)号:US20240204764A1
公开(公告)日:2024-06-20
申请号:US18065768
申请日:2022-12-14
Applicant: GlobalFoundries U.S. Inc.
Inventor: Santosh Sharma , Johnatan Avraham Kantarovsky , Rajendran Krishnasamy
CPC classification number: H03K17/08 , H01L29/404 , H01L29/7816
Abstract: An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.
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公开(公告)号:US20220181361A1
公开(公告)日:2022-06-09
申请号:US17113418
申请日:2020-12-07
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: John J. Ellis-Monaghan , Steven M. Shank , Rajendran Krishnasamy , Ramsey Hazbun
IPC: H01L27/144 , H01L31/028 , H01L31/0312 , H01L31/103 , H01L31/18
Abstract: Structures including multiple photodiodes and methods of fabricating a structure including multiple photodiodes. A substrate has a first trench extending to a first depth into the substrate and a second trench extending to a second depth into the substrate that is greater than the first depth. A first photodiode includes a first light-absorbing layer containing a first material positioned in the first trench. A second photodiode includes a second light-absorbing layer containing a second material positioned in the second trench. The first material and the second material each include germanium.
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公开(公告)号:US11316019B2
公开(公告)日:2022-04-26
申请号:US16942734
申请日:2020-07-29
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Johnatan Avraham Kantarovsky , Rajendran Krishnasamy , Siva P. Adusumilli , Steven Bentley , Michael Joseph Zierak , Jeonghyun Hwang
IPC: H01L29/40 , H01L29/778 , H01L29/66 , H01L29/423 , H01L29/78
Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.
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公开(公告)号:US20240282852A1
公开(公告)日:2024-08-22
申请号:US18171765
申请日:2023-02-21
Applicant: GlobalFoundries U.S. Inc.
Inventor: Shesh Mani Pandey , Kaustubh Shanbhag , Rajendran Krishnasamy , Judson R. Holt
IPC: H01L29/78 , H01L21/306 , H01L21/308 , H01L29/06 , H01L29/66
CPC classification number: H01L29/7816 , H01L21/30604 , H01L21/308 , H01L29/0642 , H01L29/66681
Abstract: Disclosed are embodiments of a structure including a semiconductor layer and a device, which has a well region within the semiconductor layer and at least one porous region within and shallower in depth than the well region. In some embodiments, the device can be a field effect transistor (FET) (e.g., a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFETs)) with a drain drift region that extends through the well region around the porous region(s) to a drain region. The porous region(s) can modify the electric field in this drain drift region, thereby improving device performance. Embodiments can vary with regard to the number, size, shape, configuration, etc. of the porous region(s) within the well region. Also disclosed herein are method embodiments for forming the semiconductor structure.
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公开(公告)号:US20240074167A1
公开(公告)日:2024-02-29
申请号:US17895156
申请日:2022-08-25
Applicant: GlobalFoundries U.S. Inc.
Inventor: Anindya Nath , Ephrem G. Gebreselasie , Rajendran Krishnasamy , Alain F. Loiseau
IPC: H01L27/112 , H01L23/525 , H01L29/735
CPC classification number: H01L27/11206 , H01L23/5256 , H01L29/735
Abstract: Embodiments of the disclosure provide a circuit structure including an electrically programmable fuse (efuse) and lateral bipolar transistor. A structure of the disclosure includes a lateral bipolar transistor within a semiconductor layer and over a substrate. An insulator layer is over a portion of the semiconductor layer. An efuse structure is within a polycrystalline semiconductor layer and over the insulator layer. The efuse structure is over a current path through the lateral bipolar transistor.
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公开(公告)号:US20240063315A1
公开(公告)日:2024-02-22
申请号:US17820979
申请日:2022-08-19
Applicant: GlobalFoundries U.S. Inc.
Inventor: Siva P. Adusumilli , Ramsey Hazbun , John J. Ellis-Monaghan , Rajendran Krishnasamy
IPC: H01L31/0232 , H01L31/028 , H01L31/105 , H01L31/18
CPC classification number: H01L31/02327 , H01L31/028 , H01L31/105 , H01L31/1808
Abstract: A photodetector structure includes a first semiconductor material layer over a doped well in a substrate. The photodetector structure includes an air gap vertically between the first semiconductor material layer and a first portion of the doped well. The photodetector structure includes an insulative collar on the first portion of the doped well and laterally surrounding the air gap. The photodetector structure may include a second semiconductor material layer on the first portion of the doped well and laterally surrounded by the insulative collar. The photodetector structure may include a third semiconductor layer over the first semiconductor layer.
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公开(公告)号:US20230402447A1
公开(公告)日:2023-12-14
申请号:US17806797
申请日:2022-06-14
Applicant: GlobalFoundries U.S. Inc.
Inventor: Anindya Nath , Alain F. Loiseau , Rajendran Krishnasamy , Souvick Mitra
CPC classification number: H01L27/0248 , H01L29/87
Abstract: Disclosed are a structure and method. The structure includes a substrate having monocrystalline lower and upper portions and a high resistance portion (e.g., a trap-rich amorphous portion) between the lower and upper portions. An isolation region extends through the upper portion, is above the high resistance portion, and is positioned laterally adjacent to a device section of the upper portion also above the high resistance portion. One or more devices (e.g., a diode, multiple diodes, a diode string, multiple diode strings, etc.) are on the trench isolation region, on the device section, and/or within the device section. The device(s) are separated from the lower portion by the high resistance portion and, potentially, by the isolation region or the device section. Such device(s) can be employed for electrostatic discharge (ESD) protection on RFIC chips and can sustain a larger RF voltage, provide area savings, reduce parasitic capacitance, improve harmonics, etc.
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