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    Methods for repairing defects on a semiconductor substrate
    42.
    发明授权
    Methods for repairing defects on a semiconductor substrate 有权
    用于修复半导体衬底上的缺陷的方法

    公开(公告)号：US06582579B1

    公开(公告)日：2003-06-24

    申请号：US09534704

    申请日：2000-03-24

    Applicant: Cyprian Uzoh

    Inventor： Cyprian Uzoh

    IPC: C25D502

    CPC classification number: H01L21/76877 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76892

    Abstract: The present invention relates to methods for repairing defects on a semiconductor substrate. This is accomplished by selectively depositing the conductive material in defective portions in the cavities while removing residual portions from the field regions of the substrate. Another method according to the present invention includes forming a uniform conductive material overburden on a top surface of the substrate. The present invention also discloses a method for depositing a second conductive material on the first conductive material of the substrate.

    Abstract translation: 本发明涉及修复半导体衬底上的缺陷的方法。 这是通过在空腔中的缺陷部分中选择性地沉积导电材料而实现的，同时从衬底的场区域去除残余部分。 根据本发明的另一种方法包括在衬底的顶表面上形成均匀的导电材料覆盖层。 本发明还公开了一种在衬底的第一导电材料上沉积第二导电材料的方法。

    LOW STRESS VIAS
    46.
    发明申请
    LOW STRESS VIAS 有权
    低应力VIAS

    公开(公告)号：US20130026645A1

    公开(公告)日：2013-01-31

    申请号：US13193814

    申请日：2011-07-29

    Applicant: Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    Inventor： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    IPC: H01L23/48 ,  H01L21/283

    CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2224/10135 ,  H01L2924/07811 ,  H01L2924/00

    Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

    Abstract translation: 部件可以包括具有远离其前表面和后表面的基板，从后表面朝向前表面延伸的开口以及在开口内延伸的导电通孔。 基底可以具有小于10ppm /℃的CTE。开口可以限定前表面和后表面之间的内表面。 导电通孔可以包括覆盖在内表面上的第一金属层和覆盖第一金属层并电耦合到第一金属层的第二金属区域。 第二金属区域可具有大于第一金属层的CTE的CTE。 导电通孔可以在导电通孔的直径上具有小于第二金属区域的CTE的80％的有效CTE。

    SINGLE EXPOSURE IN MULTI-DAMASCENE PROCESS
    47.
    发明申请
    SINGLE EXPOSURE IN MULTI-DAMASCENE PROCESS 有权
    多元化过程中的单次接触

    公开(公告)号：US20120326313A1

    公开(公告)日：2012-12-27

    申请号：US13170095

    申请日：2011-06-27

    Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba

    Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba

    IPC: H01L23/52 ,  H01L21/768

    CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.

    Abstract translation: 仅使用单个或减少数量的曝光步骤来制造多层半导体器件的方法，例如多层镶嵌或倒置的多层镶嵌结构。 该方法可以包括用于对于给定的去除条件蚀刻由具有差异去除速率的材料形成的前体结构。 该方法可以包括在不同的去除条件下从多层结构去除材料。 还公开了具有不同尺寸的多个空腔的多层镶嵌结构。 空腔可以具有平滑的内壁表面。 结构的层可以直接接触。 空腔可以用导电金属或绝缘体填充。 进一步公开了使用这些方法和结构的多层半导体器件。

    Low stress vias
    48.
    发明授权
    Low stress vias 有权
    低压通孔

    公开(公告)号：US08816505B2

    公开(公告)日：2014-08-26

    申请号：US13193814

    申请日：2011-07-29

    Applicant: Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    Inventor： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    IPC: H01L23/48 ,  H01L21/283

    CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2224/10135 ,  H01L2924/07811 ,  H01L2924/00

    Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

    Abstract translation: 部件可以包括具有远离其前表面和后表面的基板，从后表面朝向前表面延伸的开口以及在开口内延伸的导电通孔。 基底可以具有小于10ppm /℃的CTE。开口可以限定前表面和后表面之间的内表面。 导电通孔可以包括覆盖在内表面上的第一金属层和覆盖第一金属层并电耦合到第一金属层的第二金属区域。 第二金属区域可具有大于第一金属层的CTE的CTE。 导电通孔可以在导电通孔的直径上具有小于第二金属区域的CTE的80％的有效CTE。

    Systems and methods for producing flat surfaces in interconnect structures
    50.
    发明授权
    Systems and methods for producing flat surfaces in interconnect structures 有权
    用于在互连结构中产生平坦表面的系统和方法

    公开(公告)号：US08728934B2

    公开(公告)日：2014-05-20

    申请号：US13168839

    申请日：2011-06-24

    Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

    Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

    IPC: H01L21/4763

    CPC classification number: H01L21/76898 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/7688 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

    Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有共面或平坦的顶表面。 另一个特征是形成互连结构的方法，其导致互连结构具有相对于衬底顶表面向上倾斜大于零的表面。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

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