公开(公告)号：US20230080522A1

公开(公告)日：2023-03-16

申请号：US17932582

申请日：2022-09-15

Applicant: IMEC VZW

Inventor： Eric Beyne ,  Anne Jourdain ,  Anabela Veloso

IPC: H01L23/528 ,  H01L23/522

Abstract: An integrated circuit (IC) chip is provided. In one aspect, a semiconductor substrate includes active devices on its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to the power rails by a plurality of Through Semiconductor Via connections, which run from the power rails to the back of the substrate. The TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and any power delivery track directly adjacent to the power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. A method of producing an IC chip includes producing the slit-shaped TSVs before the buried power rails.

公开(公告)号：US11362061B2

公开(公告)日：2022-06-14

申请号：US16906387

申请日：2020-06-19

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Lin Hou ,  Jaber Derakhshandeh ,  Eric Beyne ,  Ingrid De Wolf ,  Giovanni Capuz

IPC: H01L23/00

Abstract: A method is disclosed for electrically bonding a first semiconductor component to a second semiconductor component, both components including arrays of contact areas. In one aspect, prior to bonding, layers of an intermetallic compound are formed on the contact areas of the second component. The roughness of the intermetallic layers is such that the intermetallic layers include cavities suitable for insertion of a solder material in the cavities, under the application of a bonding pressure, when the solder is at a temperature below its melting temperature. The components are aligned and bonded, while the solder material is applied between the two. Bonding takes place at a temperature below the melting temperature of the solder. The bond can be established only by the insertion of the solder into the cavities of the intermetallic layers, and without the formation of a second intermetallic layer.

公开(公告)号：US20220037283A1

公开(公告)日：2022-02-03

申请号：US17387617

申请日：2021-07-28

Applicant: IMEC VZW

Inventor： Joeri De Vos ,  Eric Beyne

IPC: H01L23/00 ,  H01L23/538 ,  H01L27/06

Abstract: A substrate, assembly and method for bonding and electrically interconnecting substrates are provided. According to the method, two substrates are provided, each comprising metal contact structures that are electrically isolated from each other by a bonding layer of dielectric material. Openings are produced in the bonding layer, the openings lying within the surface area of the respective contact structures, exposing the contact material of the structures at the bottom of the openings. Then a layer of conductive material is deposited, filling the openings, after which the material is planarized, removing it from the surface of the bonding layer and leaving a recessed contact patch in the openings. The substrates are then aligned, brought into contact, and bonded by applying an annealing step at a temperature suitable for causing thermal expansion of the contact structures. Deformation of the conductive material of the contact structures through creep pushes the material into the openings from the bottom up, thereby bringing the contact patches into mutual and conductive contact.

公开(公告)号：US20200152508A1

公开(公告)日：2020-05-14

申请号：US16675080

申请日：2019-11-05

Applicant: IMEC vzw

Inventor： Anne Jourdain ,  Nouredine Rassoul ,  Eric Beyne

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/463 ,  H01L21/48 ,  H01L21/308

Abstract: A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.

公开(公告)号：US10170450B2

公开(公告)日：2019-01-01

申请号：US15697285

申请日：2017-09-06

Applicant: IMEC VZW

Inventor： Eric Beyne ,  Joeri De Vos ,  Stefaan Van Huylenbroeck

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48 ,  H01L21/3065

Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.

公开(公告)号：US20170005000A1

公开(公告)日：2017-01-05

申请号：US15199147

申请日：2016-06-30

Applicant: IMEC vzw

Inventor： Eric Beyne

IPC: H01L21/768 ,  H01L25/065 ,  H01L23/00 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76898 ,  H01L21/02063 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/481 ,  H01L24/80 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/1036 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06544 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly. The IC device or devices in the upper wafer or wafers have contact structures that serve as masks for the etching of the TSV opening. A conformal isolation liner is deposited in the TSV opening, and subsequently removed from the bottom and any horizontal areas in the TSV opening, while maintaining the liner on the sidewalls, followed by deposition of a TSV plug in the TSV opening. The removal of the liner is done without applying a lithography step.

Abstract translation: 公开了一种用于将布置在诸如硅晶片的基板上的两个或更多个IC器件接合和​​互连的方法。 在一个方面，通过直接接合技术将晶片接合以形成晶片组件，并且多个IC器件设置有金属接触结构。 通过接合晶片组件制造TSV（Through Semiconductor Via）。 上部晶片或晶片中的IC器件或器件具有用作蚀刻TSV开口的掩模的接触结构。 保形隔离衬垫沉积在TSV开口中，随后从TSV开口中的底部和任何水平区域移除，同时将衬垫保持在侧壁上，随后在TSV开口中沉积TSV插头。 在不应用光刻步骤的情况下完成衬垫的去除。