公开(公告)号：US20250118564A1

公开(公告)日：2025-04-10

申请号：US18906945

申请日：2024-10-04

Applicant: IMEC VZW

Inventor： Eric Beyne ,  Liesbeth Witters

IPC: H01L21/306 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/768

Abstract: A layer of semiconductor devices is produced on the frontside of a crystalline semiconductor substrate, in regions separated by dielectric-filled cavities formed previously. Additional layers are then formed on the device layer. The substrate is then flipped and bonded face down to a second substrate, following by the thinning of the crystalline first substrate from the backside. The thinning proceeds as far as possible without removing the full thickness of the first substrate anywhere across its surface. After this, an anisotropic etch is performed to remove additional material of the first substrate. The in-plane dimensions of the device regions separated by the dielectric-filled cavities are specified so that the anisotropic etch is stopped by a crystallographic plane of the substrate material or by the dielectric material in the cavities, before it can reach the devices on the frontside.

公开(公告)号：US20240297136A1

公开(公告)日：2024-09-05

申请号：US18591705

申请日：2024-02-29

Applicant: IMEC VZW

Inventor： Jaber Derakhshandeh ,  Vadiraj Manjunath Ananthapadmanabha Rao ,  Danny Wan ,  Eric Beyne ,  Kristiaan De Greve ,  Anton Potocnik

IPC: H01L23/00 ,  H10N60/01 ,  H10N60/81

CPC classification number: H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H10N60/0912 ,  H10N60/815 ,  H01L2224/0401 ,  H01L2224/11009 ,  H01L2224/11462 ,  H01L2224/13109

Abstract: Superconducting solder bumps are produced on a qubit substrate by electrodeposition. The substrate comprises qubit areas, and superconducting contact pads connected to the qubit areas. First a protection layer is formed on the substrate, and patterned so as to cover at least the qubit areas. Then one or more thin layers are deposited conformally on the patterned protection layer, the thin layers comprising at least a non-superconducting layer suitable for acting as a seed layer for the electrodeposition of the solder bumps. The seed layer is removed locally in areas which lie within the surface area of respective contact pads. This is done by producing and patterning a mask layer, so that openings are formed therein, and by removing the seed layer from the bottom of the openings. The solder bumps are formed by electrodeposition of the solder material on the bottom of the openings. After the formation of the solder bumps, the seed layer and the protection layer are removed.

公开(公告)号：US20240203965A1

公开(公告)日：2024-06-20

申请号：US18538422

申请日：2023-12-13

Applicant: IMEC VZW

Inventor： Jaber Derakhshandeh ,  Eric Beyne

IPC: H01L25/16 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/162 ,  H01L21/7684 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method for bonding and interconnecting micro-electronic components is provided. In one aspect, two substrates are bonded to form a 3D assembly of micro-electronic components. Both substrates include first cavities open to the respective bonding surfaces, and at least one substrate includes a second cavity that is larger than the first cavities in terms of its in-plane dimensions, and possibly also in terms of its depth. An electrically conductive layer is produced on each substrate. The layer is patterned in the second cavity, and a micro-electronic device is fabricated in the second cavity. The bonding surfaces are planarized, removing the conformal layer from the bonding surfaces, and the substrates are bonded to form the assembly, where the first cavities of both substrates are brought into mutual contact to form an electrical connection. Device in the large cavities may be contacted through TSV connections or back end of line interconnect levels.

公开(公告)号：US11367705B2

公开(公告)日：2022-06-21

申请号：US16719680

申请日：2019-12-18

Applicant: IMEC VzW

Inventor： Eric Beyne

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

Abstract: A method of using sacrificial structures in a mold substrate for packaging a first die and one or more second dies or stacks thereof is disclosed. The method allows testing of the first die prior to mounting the second dies, without requiring a TSV insert. In one aspect, a block of sacrificial material is embedded together with the first die in a first mold substrate and to one side of the first die. The removal of the block creates an opening. The method is configured so that contacts are exposed at the bottom of the opening, the contacts being electrically connected to corresponding contacts on the first die. This may be realized by bonding both the die and the sacrificial block to a redistribution layer, or by mounting a bridge device between the first die and the block prior to a first overmolding applied for producing the first mold substrate. A second die or a stack of second dies is mounted in the opening and bonded to the exposed contacts, after which a second mold substrate is produced, embedding the second die or dies.

公开(公告)号：US20210098299A1

公开(公告)日：2021-04-01

申请号：US17038737

申请日：2020-09-30

Applicant: IMEC VZW

Inventor： Frank Holsteyns ,  Eric Beyne ,  Christophe Lorant ,  Simon Braun

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48

Abstract: A method is provided for dicing a semiconductor substrate into a plurality of dies, the semiconductor substrate having a front side including a plurality of device areas, a back side, and a plurality of through substrate vias. The method includes defining, from the front side, at least one trench to be formed between adjacent device areas, forming the at least one trench, from the front side of the semiconductor substrate, arranging a protective layer on the front side of the semiconductor substrate, thinning the semiconductor substrate from the back side to reduce the thickness of the semiconductor substrate, processing the back side of the semiconductor substrate to form at least one contact, the contact contacting at least one through substrate via, etching through the minor portion of the thickness of the semiconductor substrate underneath the at least one trench, and dicing the semiconductor substrate into the plurality of dies.

公开(公告)号：US10797016B2

公开(公告)日：2020-10-06

申请号：US15798939

申请日：2017-10-31

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Vikas Dubey ,  Eric Beyne ,  Giovanni Capuz

IPC: H01L23/00

Abstract: A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.

公开(公告)号：US10141284B2

公开(公告)日：2018-11-27

申请号：US15604454

申请日：2017-05-24

Applicant: IMEC VZW

Inventor： Soon-Wook Kim ,  Lan Peng ,  Patrick Verdonck ,  Robert Miller ,  Gerald Peter Beyer ,  Eric Beyne

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/02 ,  H01L21/3105

Abstract: The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

公开(公告)号：US20180247914A1

公开(公告)日：2018-08-30

申请号：US15908641

申请日：2018-02-28

Applicant: IMEC VZW

Inventor： Lan Peng ,  Soon-Wook Kim ,  Eric Beyne ,  Gerald Peter Beyer ,  Erik Sleeckx ,  Robert Miller

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L24/83 ,  H01J37/32091 ,  H01J37/321 ,  H01J2237/334 ,  H01L21/2007 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29082 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/83009 ,  H01L2224/83011 ,  H01L2224/83022 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2224/83986 ,  H01L2924/04642 ,  H01L2924/059 ,  H01L2924/20106 ,  H01L2924/20107

Abstract: The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient. The method additionally includes bonding the first and the second substrates by contacting the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate to form a substrate assembly. The method further includes post-bond annealing the assembly.

公开(公告)号：US20230200263A1

公开(公告)日：2023-06-22

申请号：US18060389

申请日：2022-11-30

Applicant: IMEC VZW

Inventor： Jaber Derakhshandeh ,  Iuliana Radu ,  Eric Beyne ,  Bogdan Govoreanu

IPC: H10N69/00 ,  H01L23/00 ,  H01L23/538

CPC classification number: H10N69/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/05 ,  H01L24/08 ,  H01L23/5384 ,  H01L24/14 ,  H01L24/06 ,  H01L2224/13109 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/05609 ,  H01L2224/08225 ,  H01L2224/0557 ,  H01L2224/06181

Abstract: The present disclosure relates to a quantum bit (qubit) chip. The qubit chip includes two or more qubit wafers arranged along a common axis and one or more spacer elements. The spacer elements and the qubit wafers are alternately arranged on the common axis. The qubit chip further includes a conductive arrangement configured to electrically connect the two or more qubit wafers, where the conductive arrangement includes at least one superconducting via per each qubit wafer of the two or more qubit wafers and each spacer element of the one or more spacer elements, the at least one superconducting via passing through the qubit wafer or spacer element.

公开(公告)号：US10985057B2

公开(公告)日：2021-04-20

申请号：US16675080

申请日：2019-11-05

Applicant: IMEC vzw

Inventor： Anne Jourdain ,  Nouredine Rassoul ,  Eric Beyne

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/321 ,  H01L21/463 ,  H01L21/48 ,  H01L23/538

Abstract: A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.