公开(公告)号：US20170076970A1

公开(公告)日：2017-03-16

申请号：US15359620

申请日：2016-11-23

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Rainer Leuschner ,  Bernhard Goller ,  Bernhard Boche ,  Manfred Engelhardt ,  Hermann Wendt ,  Bernd Noehammer ,  Karl Mayer ,  Michael Roesner ,  Monika Cornelia Voerckel

IPC: H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L21/285 ,  H01L21/304 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/6835 ,  H01L21/0331 ,  H01L21/283 ,  H01L21/2855 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/0001

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Abstract translation: 用于处理半导体工件的方法可以包括提供包括一个或多个切口区域的半导体工件; 通过从所述工件的第一侧移除来自所述一个或多个切割区域的材料，在所述工件中形成一个或多个沟槽; 将具有第一侧的工件安装到载体上; 从工件的第二侧使工件变薄; 以及在所述工件的第二侧上形成金属化层。

公开(公告)号：US09355881B2

公开(公告)日：2016-05-31

申请号：US14182689

申请日：2014-02-18

Applicant: Infineon Technologies AG

Inventor： Bernhard Goller ,  Eva-Maria Hess ,  Edward Fuergut ,  Christian Schweiger

IPC: H01L21/683 ,  H01L21/268 ,  H01L21/304 ,  H01L21/762 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/6835 ,  H01L21/268 ,  H01L21/304 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76251 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/02 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/82106 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00 ,  H01L2224/82 ,  H05K3/467 ,  H01L2224/03 ,  H01L2924/01029

Abstract: A method for manufacturing a semiconductor device includes providing a carrier and a semiconductor wafer having a first side and a second side opposite to the first side. The method includes applying a dielectric material to the carrier or the semiconductor wafer and bonding the semiconductor wafer to the carrier via the dielectric material. The method includes processing the semiconductor wafer and removing the carrier from the semiconductor wafer such that the dielectric material remains on the semiconductor wafer to provide a semiconductor device comprising the dielectric material.

Abstract translation: 一种制造半导体器件的方法包括提供具有第一侧和与第一侧相对的第二侧的载流子和半导体晶片。 该方法包括将介电材料施加到载体或半导体晶片，并通过电介质材料将半导体晶片接合到载体上。 该方法包括处理半导体晶片并从半导体晶片去除载体，使得介电材料保留在半导体晶片上，以提供包括电介质材料的半导体器件。

公开(公告)号：US20150280287A1

公开(公告)日：2015-10-01

申请号：US14230056

申请日：2014-03-31

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Alexander Breymesser ,  Bernhard Goller ,  Kamil Karlovsky ,  Francisco Javier Santos Rodriguez ,  Peter Zorn

IPC: H01M10/42 ,  H01M2/02

Abstract: A battery includes a first substrate having a first main surface, a second substrate made of a conducting material or semiconductor material, and a carrier of an insulating material. The carrier has a first and a second main surfaces, the second substrate being attached to the first main surface of the carrier. An opening is formed in the second main surface of the carrier to uncover a portion of a second main surface of the second substrate. The second main surface of the carrier is attached to the first substrate, thereby forming a cavity. The battery further includes an electrolyte disposed in the cavity.

Abstract translation: 电池包括具有第一主表面的第一基底，由导电材料或半导体材料制成的第二基底和绝缘材料的载体。 载体具有第一和第二主表面，第二基底附接到载体的第一主表面。 在载体的第二主表面上形成开口以露出第二基板的第二主表面的一部分。 载体的第二主表面附接到第一基板，从而形成空腔。 电池还包括设置在空腔中的电解质。

公开(公告)号：US20140339313A1

公开(公告)日：2014-11-20

申请号：US13896676

申请日：2013-05-17

Applicant: Infineon Technologies AG

Inventor： Dirk Hammerschmidt ,  Bernhard Goller ,  Gerald Holweg ,  Thomas Herndl

IPC: G06K19/07 ,  G06K19/073

CPC classification number: G06K19/07758 ,  G06K19/0704 ,  G06K19/0705 ,  G06K19/0717 ,  G06K19/0723 ,  G06K19/073

Abstract: A semiconductor device includes a semiconductor substrate, a battery attached to the semiconductor substrate, and a sensor attached to the semiconductor substrate. The battery is electrically connected to the sensor and configured to supply the sensor with electrical power.

Abstract translation: 半导体器件包括半导体衬底，附接到半导体衬底的电池和附接到半导体衬底的传感器。 电池电连接到传感器并且被配置为向传感器提供电力。

公开(公告)号：US20230395394A1

公开(公告)日：2023-12-07

申请号：US18236434

申请日：2023-08-22

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Alexander Breymesser ,  Bernhard Goller ,  Matthias Kuenle ,  Helmut Oefner ,  Francisco Javier Santos Rodriguez ,  Stephan Voss

IPC: H01L21/324 ,  H01L21/78 ,  H01L21/265

CPC classification number: H01L21/3247 ,  H01L21/7806 ,  H01L21/26506

Abstract: A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.

公开(公告)号：US20230330769A1

公开(公告)日：2023-10-19

申请号：US18336643

申请日：2023-06-16

Applicant: Infineon Technologies AG

Inventor： Ralf Rieske ,  Alexander Binter ,  Wolfgang Diewald ,  Bernhard Goller ,  Heimo Graf ,  Gerald Lackner ,  Jan Richter ,  Roland Rupp ,  Guenter Schagerl ,  Marko David Swoboda

IPC: B23K26/0622 ,  H01L21/02 ,  B23K26/00 ,  H01L21/78

CPC classification number: B23K26/0624 ,  H01L21/02378 ,  B23K26/0006 ,  H01L21/7813

Abstract: Provided is a machining apparatus including a profile sensor unit configured to obtain shape information about a parent substrate; and a laser scan unit configured to direct a laser beam onto the parent substrate, wherein a laser beam axis of the laser beam is tilted to an exposed main surface of the parent substrate, and wherein a track of the laser beam on the parent substrate is controllable as a function of the shape information obtained from the profile sensor unit.

公开(公告)号：US20220310380A1

公开(公告)日：2022-09-29

申请号：US17841781

申请日：2022-06-16

Applicant: Infineon Technologies AG

Inventor： Sophia Friedler ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

IPC: H01L21/02 ,  H01L21/465 ,  H01L21/8258

Abstract: A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.

公开(公告)号：US11373857B2

公开(公告)日：2022-06-28

申请号：US16411784

申请日：2019-05-14

Applicant: Infineon Technologies AG

Inventor： Bernhard Goller ,  Iris Moder ,  Petra Fischer

IPC: H01L21/02 ,  H01L29/16 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/304 ,  H01L21/3065

Abstract: One or more semiconductor manufacturing methods and/or semiconductor arrangements are provided. In an embodiment, a silicon carbide (SiC) layer is provided. The SiC layer has a first portion overlying a second portion. The first portion has a first side distal the second portion and a second side proximal the second portion. The first portion is converted into a porous layer overlying the second portion. The porous layer has a first side distal the second portion and a second side proximal the second portion. The porous layer is removed to expose a first side of the second portion. After removing the porous layer, the first side of the second portion has a surface roughness less than a surface roughness of the first side of the first portion and/or less than a surface roughness of the first side of the porous layer.

公开(公告)号：US20210391377A1

公开(公告)日：2021-12-16

申请号：US17345534

申请日：2021-06-11

Applicant: Infineon Technologies AG

Inventor： Alexander Frey ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri ,  Alfred Sigl ,  Tobias Weindler

IPC: H01L27/146 ,  H01L23/544 ,  H01L21/304 ,  H01L29/78 ,  G01S17/894

Abstract: A method of manufacturing a semiconductor device is described. The method includes providing a semiconductor substrate. The semiconductor substrate includes a high-doped semiconductor substrate layer, a high-doped semiconductor device layer, and a low-doped semiconductor etch stop layer arranged between the high-doped semiconductor substrate layer and the high-doped semiconductor device layer. The high-doped semiconductor substrate layer is removed, wherein the removing includes dopant selective chemical etching stopping at the low-doped semiconductor etch stop layer. Further, the low-doped semiconductor etch stop layer is thinned to generate an exposed surface of the high-doped semiconductor device layer.

公开(公告)号：US20210391218A1

公开(公告)日：2021-12-16

申请号：US17343885

申请日：2021-06-10

Applicant: Infineon Technologies AG

Inventor： Felix Johannes Heinrich Ernst ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/225 ,  H01L29/06 ,  H01L23/14

Abstract: A method of manufacturing a semiconductor device is described. A semiconductor substrate is provided. The semiconductor substrate includes a semiconductor substrate layer and a semiconductor device layer. The method includes transforming areas of the semiconductor device layer into dicing areas which can be removed by etching, and removing the semiconductor substrate layer and the dicing areas by using etching.