公开(公告)号：US10141311B2

公开(公告)日：2018-11-27

申请号：US15115852

申请日：2014-03-24

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy

IPC: H01L27/092 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/8238

Abstract: Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.

公开(公告)号：US10074573B2

公开(公告)日：2018-09-11

申请号：US15411095

申请日：2017-01-20

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

Abstract: Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

公开(公告)号：US20180248028A1

公开(公告)日：2018-08-30

申请号：US15755489

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Matthew V. Metz ,  Harold W. Kennel ,  Gilbert Dewey ,  Willy Rachmady ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L27/092

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02538 ,  H01L21/02639 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/778

Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.

公开(公告)号：US09893149B2

公开(公告)日：2018-02-13

申请号：US14935971

申请日：2015-11-09

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Anand S. Murthy ,  Glenn A. Glass ,  Daniel B. Aubertine ,  Tahir Ghani ,  Jack T. Kavalieros ,  Roza Kotlyar

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L21/762 ,  H01L29/16 ,  H01L29/161 ,  H01L29/08

CPC classification number: H01L29/1054 ,  H01L21/76224 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

公开(公告)号：US20170222052A1

公开(公告)日：2017-08-03

申请号：US15489423

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Cory E. Weber ,  Mark Y. Liu ,  Anand S. Murthy ,  Hemant V. Deshpande ,  Daniel B. Aubertine

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/16 ,  H01L29/417 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

公开(公告)号：US09343559B2

公开(公告)日：2016-05-17

申请号：US14690615

申请日：2015-04-20

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Kelin J. Kuhn ,  Seiyon Kim ,  Anand S. Murthy ,  Daniel B. Aubertine

IPC: H01L29/775 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0676 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7855 ,  H01L29/78696

Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

公开(公告)号：US20160071934A1

公开(公告)日：2016-03-10

申请号：US14935971

申请日：2015-11-09

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Anand S. Murthy ,  Glenn A. Glass ,  Daniel B. Aubertine ,  Tahir Ghani ,  Jack T. Kavalieros ,  Roza Kotlyar

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L29/1054 ,  H01L21/76224 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

公开(公告)号：US12288803B2

公开(公告)日：2025-04-29

申请号：US18540544

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC: H01L29/06 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US20250022878A1

公开(公告)日：2025-01-16

申请号：US18903242

申请日：2024-10-01

Applicant: Intel Corporation

Inventor： Andy Chih-Hung Wei ,  Anand S. Murthy ,  Mauro J. Kobrinsky ,  Guillaume Bouche

IPC: H01L27/088 ,  H01L23/522 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.

公开(公告)号：US12170319B2

公开(公告)日：2024-12-17

申请号：US17033362

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Kevin Cook ,  Anand S. Murthy ,  Gilbert Dewey ,  Nazila Haratipour ,  Ralph Thomas Troeger ,  Christopher J. Jezewski ,  I-Cheng Tung

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.