公开(公告)号：US11984487B2

公开(公告)日：2024-05-14

申请号：US16892447

申请日：2020-06-04

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Guillaume Bouche

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  B82Y10/00

CPC classification number: H01L29/4238 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  B82Y10/00

Abstract: Disclosed herein are non-planar transistor (e.g., nanoribbon) arrangements having asymmetric gate enclosures on at least one side. An example transistor arrangement includes a channel material shaped as a nanoribbon, and a gate stack wrapping around at least a portion of a first face of the nanoribbon, a sidewall, and a portion of a second face of the nanoribbon. Portions of the gate stack provided over the first and second faces of the nanoribbon extend in a direction parallel to the longitudinal axis of the nanoribbon for a certain distance that may be referred to as a “gate length.” A portion of the gate stack wrapping around the sidewall of the nanoribbon does not extend along the entire gate length, but, rather, extends over less than a half of the gate length, e.g., about one third of the gate length, thus making the gate enclosure on that sidewall asymmetric.

公开(公告)号：US11929435B2

公开(公告)日：2024-03-12

申请号：US17899429

申请日：2022-08-30

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/2003 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US11672133B2

公开(公告)日：2023-06-06

申请号：US16447603

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Patrick R. Morrow ,  Hui Jae Yoo ,  Sean T. Ma ,  Scott B. Clendenning ,  Abhishek A. Sharma ,  Ehren Mannebach ,  Urusa Alaan

IPC: H10B63/00 ,  H01L21/311 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B63/845 ,  H01L21/31116 ,  H01L21/7682 ,  H10B41/27 ,  H10B43/27

Abstract: A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.

公开(公告)号：US20230057464A1

公开(公告)日：2023-02-23

申请号：US17981561

申请日：2022-11-07

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Aaron D. Lilak ,  Abhishek A. Sharma ,  Van H. Le ,  Seung Hoon Sung ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L27/108 ,  H01L21/822 ,  H01L23/528 ,  H01L49/02 ,  H01L29/06

Abstract: Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.

公开(公告)号：US11482524B2

公开(公告)日：2022-10-25

申请号：US16831681

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Sean T. Ma

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first dielectric material continuously around the first gate metal; and a second dielectric material continuously around the second gate metal, wherein the first dielectric material and the second dielectric material are present between the first gate metal and the second gate metal.

公开(公告)号：US11367789B2

公开(公告)日：2022-06-21

申请号：US16316337

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Sean T. Ma ,  Harold Kennel

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/778 ,  H01L29/10 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00

Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.

公开(公告)号：US11276755B2

公开(公告)日：2022-03-15

申请号：US16303654

申请日：2016-06-17

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L21/70 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

Abstract: Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.

公开(公告)号：US20210384307A1

公开(公告)日：2021-12-09

申请号：US16891950

申请日：2020-06-03

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Cory E. Weber

IPC: H01L29/417 ,  H01L29/786 ,  H01L29/78

Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a channel region including a semiconductor material; and a source/drain region at a side face of the channel region, wherein the source/drain region includes a semiconductor portion and a contact metal, and the semiconductor portion is between the contact metal and the semiconductor material.

公开(公告)号：US20210351078A1

公开(公告)日：2021-11-11

申请号：US17385688

申请日：2021-07-26

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Sean T. Ma ,  Justin R. Weber ,  Patrick Morrow ,  Rishabh Mehandru

IPC: H01L21/822 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/683 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/167 ,  H01L29/40 ,  H01L29/66

Abstract: An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.

公开(公告)号：US20210305370A1

公开(公告)日：2021-09-30

申请号：US16831640

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Sean T. Ma

IPC: H01L29/08 ,  H01L29/06 ,  H01L23/522 ,  H01L23/535

Abstract: Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.