公开(公告)号：US09727345B2

公开(公告)日：2017-08-08

申请号：US13854001

申请日：2013-03-29

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Rinat Rappoport ,  Michael Mishaeli ,  Hisham Shafi ,  Oron Lenz ,  Jason W. Brandt ,  Stephen A. Fischer ,  Bret L. Toll ,  Inder M. Sodhi ,  Alon Naveh ,  Ganapati N. Srinivasa ,  Ashish V. Choubal ,  Scott D. Hahn ,  David A. Koufaty ,  Russell J. Fenger ,  Gaurav Khanna ,  Eugene Gorbatov ,  Mishali Naik ,  Andrew J. Herdrich ,  Abirami Prabhakaran ,  Sanjeev S. Sahagirdar ,  Paul Brett ,  Paolo Narvaez ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy

IPC: G06F9/44 ,  G06F9/455 ,  G06F9/50

CPC classification number: G06F9/4401 ,  G06F9/45558 ,  G06F9/5077 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/36

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

公开(公告)号：US09448829B2

公开(公告)日：2016-09-20

申请号：US13730491

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Gaurav Khanna ,  Russell J. Fenger ,  Bryant E. Bigbee ,  Andrew D. Henroid ,  David A. Koufaty

IPC: G06F9/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/38

CPC classification number: G06F9/45558 ,  G06F9/3885 ,  G06F9/5077 ,  G06F2009/4557

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组两个或更多个小物理处理器核; 至少一个大型物理处理器核具有相对较高性能的处理能力和相对较小的物理处理器核的相对较高的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将两个或更多个小物理处理器核心的集合暴露给软件，并从软件中隐藏至少一个大的物理处理器核心。

公开(公告)号：US09329900B2

公开(公告)日：2016-05-03

申请号：US13730539

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

IPC: G06F9/50 ,  G06F9/455 ,  G06F15/80

CPC classification number: G06F9/5044 ,  G06F9/45533 ,  G06F9/5077 ,  G06F9/5094 ,  G06F15/80 ,  Y02D10/22

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同 虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心集合内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行 从第一组或第二组物理处理器到第一虚拟处理器。

公开(公告)号：US20150007196A1

公开(公告)日：2015-01-01

申请号：US13931657

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： BRET L. TOLL ,  Jason W. Brandt ,  Eliezer Weissmann ,  Inder M. Sodhi ,  David A. Koufaty ,  Scott D. Hanh

IPC: G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/5044 ,  G06F9/5088 ,  Y02D10/22 ,  Y02D10/32

Abstract: A processor of an aspect includes a first heterogeneous physical compute element having a first set of supported instructions and architectural features, and a second heterogeneous physical compute element having a second set of supported instructions and architectural features. The second set of supported instructions and architectural features is different than the first set of supported instructions and architectural features. The processor also includes a workload and architectural state migration module coupled with the first and second heterogeneous physical compute elements. The workload and state migration module is operable to migrate a workload and associated architectural state from the first heterogeneous physical compute element to the second heterogeneous physical compute element in response to an attempt by the workload to perform at least one of an unsupported instruction and an unsupported architectural feature on the first heterogeneous physical compute element.

Abstract translation: 一方面的处理器包括具有第一组支持的指令和架构特征的第一异构物理计算元件，以及具有第二组支持的指令和架构特征的第二异构物理计算元件。 第二组支持的指令和架构特征与第一组支持的指令和架构特征不同。 处理器还包括与第一和第二异构物理计算元件耦合的工作负载和架构状态迁移模块。 工作负载和状态迁移模块可操作以响应于工作负载尝试执行不支持的指令和不支持的指令中的至少一个而将工作负载和相关联的架构状态从第一异构物理计算元件迁移到第二异构物理计算元件 第一个异构物理计算元素的架构特征。