公开(公告)号：US20240303915A1

公开(公告)日：2024-09-12

申请号：US18610369

申请日：2024-03-20

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Mrutunjayya Mrutunjayya ,  Carl S. Marshall ,  Ravishankar Iyer ,  Zack Waters

IPC: G06T15/80 ,  G06N3/08 ,  G06T15/00 ,  G06T15/10

CPC classification number: G06T15/80 ,  G06N3/08 ,  G06T15/005 ,  G06T15/10

Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

公开(公告)号：US20180373633A1

公开(公告)日：2018-12-27

申请号：US15634785

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Stephen R. Van Doren ,  Ravishankar Iyer ,  Eric R. Wehage ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Jeffrey D. Chamberlain ,  Julius Mandelblat ,  Yen-Cheng Liu ,  Stephen T. Palermo ,  Tsung-Yuan C. Tai

IPC: G06F12/0811 ,  G06F13/42 ,  G06F9/455 ,  G06F9/50 ,  G06F12/1009 ,  G06F13/16

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

公开(公告)号：US10095520B2

公开(公告)日：2018-10-09

申请号：US15194558

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： Zhen Fang ,  Xiaowei Jiang ,  Srihari Makineni ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F13/24 ,  G06F9/48

Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.

公开(公告)号：US10089229B2

公开(公告)日：2018-10-02

申请号：US15401220

申请日：2017-01-09

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Ravishankar Iyer ,  Christopher C. Gianos ,  Jeffrey D. Chamberlain ,  Ronak Singhal ,  Julius Mandelblat ,  Bret L. Toll

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0897

Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

公开(公告)号：US09870047B2

公开(公告)日：2018-01-16

申请号：US15192134

申请日：2016-06-24

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer ,  Sadagopan Srinivasan ,  Jaideep Moses ,  Srihari Makineni

IPC: G06F1/32 ,  G06F12/08 ,  H04W88/02 ,  H04W52/02 ,  G06F9/44 ,  G06F13/24 ,  G06F9/50 ,  G06F12/084

CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/4418 ,  G06F9/5094 ,  G06F12/084 ,  G06F13/24 ,  G06F2212/1028 ,  G06F2212/60 ,  G06F2212/62 ,  H04W52/028 ,  H04W88/02 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/22 ,  Y02D70/00

Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

公开(公告)号：US20170351534A1

公开(公告)日：2017-12-07

申请号：US15629882

申请日：2017-06-22

Applicant: Intel Corporation

Inventor： Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

IPC: G06F9/445 ,  G06F1/10 ,  G06F9/50 ,  G06F1/32 ,  G06F12/0891

CPC classification number: G06F9/44505 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  G06F12/0891 ,  Y02D10/128

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

公开(公告)号：US20160375372A1

公开(公告)日：2016-12-29

申请号：US14749311

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Glen J. Anderson ,  Yevgeniy Y. Yarmosh ,  David I. Poisner ,  Gregory A. Peek ,  Mark R. Francis ,  Ravishankar Iyer

IPC: A63H33/26

CPC classification number: A63H27/12 ,  A63H33/042 ,  A63H2200/00 ,  B25J9/1617 ,  B25J19/023 ,  G05B2219/40304

Abstract: Apparatuses and methods associated with block structure and robot cooperation are disclosed herein. In embodiments, a block apparatus may include a block structure-robot coordination module to cooperate with one or more robots to affect operations of the one or more robots relative to at least a block structure which the block apparatus is a member. The block apparatus may further include a housing that houses the block structure-robot coordination module, with features to mate the block apparatus with one or more other blocks to cause the block apparatus to become a member of the block structure. In embodiments, a robot may include control module to control a number of actuators to operate one or more features to perform one or more operations relative to the block structure. Other embodiments may be described and/or claimed.

Abstract translation: 本文公开了与块结构和机器人协作相关的装置和方法。 在实施例中，块装置可以包括块结构 - 机器人协调模块，以与一个或多个机器人协作，以相对于块装置是成员的至少块结构影响一个或多个机器人的操作。 块装置还可以包括容纳块结构 - 机器人协调模块的壳体，具有使块装置与一个或多个其他块配合的特征，以使块装置成为块结构的构件。 在实施例中，机器人可以包括控制模块以控制多个致动器来操作一个或多个特征以相对于块结构执行一个或多个操作。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09128842B2

公开(公告)日：2015-09-08

申请号：US13631625

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Jaideep Moses ,  Ravishankar Iyer ,  Rameshkumar G. Illikkal ,  Sadagopan Srinivasan

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/08 ,  G06F12/0891

Abstract: A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.

Abstract translation: 描述了具有高速缓存电路和逻辑电路的处理器。 逻辑电路是管理高速缓存线路的高速缓存行的输入和移除。 逻辑电路包括存储电路和控制电路。 存储电路用于存储标识高速缓存中处于修改状态的一组高速缓存行的信息。 控制电路耦合到存储电路，以响应于刷新高速缓存的信号从存储电路接收信息，并从其中确定高速缓存的地址，从而从高速缓存读取高速缓存行集合，以避免 从缓存中读取处于无效或干净状态的缓存行。

公开(公告)号：US11978155B2

公开(公告)日：2024-05-07

申请号：US17032348

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Mrutunjayya Mrutunjayya ,  Carl S. Marshall ,  Ravishankar Iyer ,  Zack Waters

IPC: G06T15/80 ,  G06N3/08 ,  G06T15/00 ,  G06T15/10

CPC classification number: G06T15/80 ,  G06N3/08 ,  G06T15/005 ,  G06T15/10

Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

公开(公告)号：US20240029455A1

公开(公告)日：2024-01-25

申请号：US18475353

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Peixi Xiong ,  Nilesh Jain ,  Ravishankar Iyer ,  Mrutunjayya Mrutunjayya

IPC: G06V20/64 ,  G06V20/70 ,  G06T15/20 ,  G06V10/56 ,  G06V10/774

CPC classification number: G06V20/64 ,  G06V20/70 ,  G06T15/20 ,  G06V10/56 ,  G06V10/774

Abstract: Systems, apparatuses and methods may provide for technology that encodes multi-view visual data into latent features via an aggregator encoder, decodes the latent features into one or more novel target views different from views of the multi-view visual data via a rendering decoder, and decodes the latent features into an object label via a label decoder. The operation to decode the latent features via the rendering decoder and to decode the latent features via the label decoder occur at least partially at the same time. The operation to encode, via the aggregator encoder, the multi-view visual data into the latent features further includes operations to: perform, via the aggregator encoder, semantic object recognition operations based on radiance field view synthesis operations, and perform, via the aggregator encoder, radiance field view synthesis operations based on semantic object recognition operations.