公开(公告)号：WO1997012399A1

公开(公告)日：1997-04-03

申请号：PCT/US1996015351

申请日：1996-09-25

Applicant: INTEL CORPORATION ,  RASTOGI, Rajiv ,  BAI, Peng ,  AHMED, Sohail ,  MEYER, William, K.

Inventor： INTEL CORPORATION

IPC: H01L23/495

CPC classification number: H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal stack (35) for use in an integrated circuit demonstrating improved electromigration properties. A base layer (31) of approximately 185 ANGSTROM of titanium is formed on an ILD followed by the formation of the bulk conductor layer (32) such as an aluminum-copper alloy layer. A capping layer (33) of approximately 185 ANGSTROM of titanium is formed on the bulk conductor layer (32). Finally, an antireflective coating (ARC) (34) of titanium nitride is formed on the capping layer (33).

Abstract translation: 一种用于集成电路的金属叠层（35），其显示出改善的电迁移特性。 在ILD上形成大约185钛的基底层（31），随后形成诸如铝 - 铜合金层的体导体层（32）。 在体导体层（32）上形成大约为185的钛的覆盖层（33）。 最后，在覆盖层（33）上形成氮化钛的抗反射涂层（ARC）（34）。

公开(公告)号：WO1997012393A1

公开(公告)日：1997-04-03

申请号：PCT/US1996015201

申请日：1996-09-23

Applicant: INTEL CORPORATION ,  BAI, Peng ,  CADIEN, Kenneth, C. ,  CHENG, Lie-Yea ,  PRINCE, Matthew, J.

Inventor： INTEL CORPORATION

IPC: H01L21/44

CPC classification number: H01L21/76801 ,  H01L21/76828

Abstract: A method of forming a novel high density interconnection structure. According to the present invention, first an insulating layer (206) is formed over a semiconductor substrate. The first insulating layer is then planarized. Next, a second insulating layer (212) is formed above the first planarized insulating layer. An opening is then etched through the first and second insulating layers. A conductive material (226) is then deposited into the opening and onto the top surface of the second insulating layer. Next, the conductive material is polished back from the second insulating layer so as to form a conductively filled opening which is substantially planar with the second insulating layer.

Abstract translation: 形成新的高密度互连结构的方法。 根据本发明，首先在半导体衬底上形成绝缘层（206）。 然后将第一绝缘层平坦化。 接着，在第一平坦化绝缘层的上方形成第二绝缘层（212）。 然后通过第一和第二绝缘层蚀刻开口。 然后将导电材料（226）沉积到开口中并沉积到第二绝缘层的顶表面上。 接下来，将导电材料从第二绝缘层抛光回去以形成与第二绝缘层基本上平面的导电填充开口。

公开(公告)号：WO1997012368A1

公开(公告)日：1997-04-03

申请号：PCT/US1996015259

申请日：1996-09-24

Applicant: INTEL CORPORATION ,  HASBUN, Robert, N. ,  JANECEK, Frank, P.

Inventor： INTEL CORPORATION

IPC: G11C07/00

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/16 ,  G11C2211/5641

Abstract: A method of performing multiple writes before erasing a memory cell (500) is described. M bits are stored in a first group of levels of the memory cell. M subsequent superseding bits are stored in a second group of levels of the memory cell (550) without erasing the memory cell. Another method of writing to a memory cell includes the step of storing m bits in a first group of levels of the memory cell. A group indicator is adjusted to identify a subsequent group of levels of the memory cell. Next, m superseding subsequent bits are stored in the subsequent group of levels, without erasing the memory cell. The steps of adjusting the group indicator and storing m superseding subsequent bits are repeated. A method of deferring an erase for a memory cell is also described. A group indicator is adjusted to identify a group of 2 adjacent levels of the memory cell available for storing an m bit value. A method of reading a memory cell includes providing a group indicator. The group indicator identifies a group of 2 adjacent levels of the memory cell. An m bit value is then read by sensing the group of 2 adjacent levels identified by the group indicator.

Abstract translation: 描述在擦除存储单元（500）之前执行多次写入的方法。 M位存储在存储器单元的第一组电平中。 M个后续替代位被存储在存储单元550的第二组电平中，而不擦除该存储单元。 写入存储器单元的另一种方法包括将m位存储在存储器单元的第一组电平中的步骤。 调整组指示符以识别存储器单元的后续组的级别。 接下来，m取代随后的比特被存储在随后的级别组中，而不擦除存储器单元。 重复调整组指示符和存储m个后续位的步骤。 还描述了延迟用于存储器单元的擦除的方法。 调整组指示符以识别可用于存储m位值的存储器单元的两个相邻级别的组。 读取存储单元的方法包括提供组指示符。 组指示符识别存储器单元的相邻两层的一组。 然后通过感测由组指示符识别的2个相邻级别的组来读取m比特值。

公开(公告)号：WO1997012367A1

公开(公告)日：1997-04-03

申请号：PCT/US1996015258

申请日：1996-09-24

Applicant: INTEL CORPORATION ,  HASBUN, Robert, N. ,  JANECEK, Franck, P.

Inventor： INTEL CORPORATION

IPC: G11C07/00

CPC classification number: G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/16 ,  G11C17/146 ,  G11C2211/5641

Abstract: A method of performing multiple writes before an erase to a nonvolatile memory cell is described. A first bit is stored at a first level of a nonvolatile memory cell (110, 120, 130 and 140). A second bit is stored at a second level of nonvolatile memory cell (110, 120, 130 and 140). A method of erasing a nonvolatile memory cell is also described. A level indicator that indicates the next level of the nonvolatile memory cell to write to is incremented. A method of reading a nonvolatile memory cell includes recalling a level indicator. The nonvolatile cell is then sensed at a level indicated by the level indicator to determine the state of the memory cell.

Abstract translation: 描述在擦除非易失性存储器单元之前执行多次写入的方法。 第一位被存储在非易失性存储单元（110,120,130和140）的第一级。 第二位存储在非易失性存储单元（110,120,130和140）的第二级。 还描述了擦除非易失性存储单元的方法。 指示写入的非易失性存储单元的下一个电平的电平指示器递增。 读取非易失性存储单元的方法包括调用电平指示符。 然后在由电平指示器指示的电平处感测非易失性单元，以确定存储单元的状态。

公开(公告)号：WO1997012329A1

公开(公告)日：1997-04-03

申请号：PCT/US1996015485

申请日：1996-09-26

Applicant: INTEL CORPORATION ,  REINHARDT, Dennis ,  BHAT, Ketan ,  JACKSON, Robert, T. ,  SENYK, Borys ,  MATTER, Eugene, P. ,  GUNTHER, Stephen, H.

Inventor： INTEL CORPORATION

IPC: G06F15/177

CPC classification number: G06F9/30083 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/30076 ,  G06F9/30185 ,  H02J9/005 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: A power control circuit and corresponding technique for reducing power consumption by an electronic device and thereby increasing performance. The power control circuit comprises a controller (120), a clock generation circuit (160) and a power supply circuit (170). The controller (120) detects whether a condition exists to scale the voltage and frequency of the electronic device and in response, signals the clock generation circuit (160) to perform frequency scaling on the electronic device and the power supply circuit (170) to perform voltage scaling on the electronic device. The condition may include a situation where the temperature of the electronic device is detected to have exceeded a thermal band. The condition may also include a situation where the electronic device is detected to be idle for a selected percentage of its run time.

Abstract translation: 一种功率控制电路和相应的技术，用于降低电子设备的功耗，从而提高性能。 功率控制电路包括控制器（120），时钟产生电路（160）和电源电路（170）。 控制器（120）检测是否存在缩放电子设备的电压和频率的条件，作为响应，信号时钟发生电路（160）在电子设备和电源电路（170）上执行频率缩放以执行 电子设备上的电压缩放。 该情况可能包括检测到电子设备的温度已经超过热带的情况。 该条件还可以包括电子设备在其运行时间的选定百分比中被检测为空闲的情况。

公开(公告)号：WO1997007657A2

公开(公告)日：1997-03-06

申请号：PCT/US1996011925

申请日：1996-07-19

Applicant: INTEL CORPORATION ,  AUCSMITH, David, W. ,  KNAUERHASE, Robert, C.

Inventor： INTEL CORPORATION

IPC: G06F21/22 ,  G06F1/00 ,  G06F21/00 ,  G09C1/00 ,  H04L9/32

CPC classification number: G06F21/64 ,  G06F21/51 ,  G06F2211/007

Abstract: A method and apparatus for access control in a computer system are disclosed. A storage unit receives a block of data having an encrypted executable image and a signature component. A separation unit coupled to the storage unit separates the signature component from the encrypted executable image. A decryption unit coupled to the separation unit decrypts the encrypted executable image using the signature component as a key. This yields a decrypted executable program. An identification unit coupled to the decryption unit locates an identification mark in the decrypted executable program and identifies a composite key assigned to the identification mark. A signature generation unit coupled to the identification unit performs a keyed cryptographic hash algorithm on the decrypted executable program using the composite key as a key. A verification unit coupled to the signature generation unit compares the signature component with the computed keyed cryptographic hash value to verify the source of the block of data and to determine whether it has been modified. If the signature matches the keyed cryptographic hash value, a rights assignment unit coupled to the verification unit assigns appropriate access rights to the decrypted executable program and allows it to be executed by a computer system.

Abstract translation: 公开了一种用于计算机系统中的访问控制的方法和装置。 存储单元接收具有加密的可执行图像和签名组件的数据块。 耦合到存储单元的分离单元将签名组件与加密的可执行映像分离。 耦合到分离单元的解密单元使用签名组件作为密钥来解密加密的可执行图像。 这产生一个解密的可执行程序。 耦合到解密单元的识别单元将解密的可执行程序中的识别标记定位并识别分配给识别标记的复合键。 耦合到识别单元的签名生成单元使用复合密钥作为密钥对解密的可执行程序执行密钥密码散列算法。 耦合到签名生成单元的验证单元将签名组件与计算的密钥加密散​​列值进行比较，以验证数据块的来源并确定其是否已被修改。 如果签名与密钥加密哈希值匹配，则与验证单元相连的权限分配单元向解密的可执行程序分配适当的访问权限，并允许其由计算机系统执行。

公开(公告)号：WO1997005550A1

公开(公告)日：1997-02-13

申请号：PCT/US1996011306

申请日：1996-07-02

Applicant: INTEL CORPORATION ,  AUCSMITH, David, W. ,  KNAUERHASE, Robert, C. ,  STANLEY, James, C.

Inventor： INTEL CORPORATION

IPC: G06F12/14

CPC classification number: G06F9/52 ,  G06F13/18

Abstract: A memory marking unit in the shared memory is read to determine whether the shared memory is currently being accessed by another processor (block 802). If the shared memory is not being accessed by another processor, a processor seeking access is granted access and changes the contents of the memory marking unit to lock out other processors from the shared memory (block 803). The last task performed on the shared memory space is identified and used to determine whether a task with high priority exists. If a task with high priority exists, the task is performed (block 804). If a task with high priority doesn't exist, the processor having access to the shared memory space accesses the shared memory space for its intended purpose (block 807). After the processor is finished accessing the shared memory space, it records the identity of the task performed (block 808) and unlocks the shared memory space (block 809).

Abstract translation: 读取共享存储器中的存储器标记单元以确定共享存储器当前是否被另一处理器访问（方框802）。 如果共享存储器未被另一个处理器访问，则授权访问的处理器被访问并且改变存储器标记单元的内容以从共享存储器锁定其他处理器（方框803）。 识别在共享内存空间上执行的最后一个任务，并用于确定是否存在具有高优先级的任务。 如果存在具有高优先级的任务，则执行任务（框804）。 如果不存在具有高优先级的任务，则具有访问共享存储器空间的处理器为其预期目的访问共享存储器空间（框807）。 在处理器完成访问共享存储器空间之后，它记录执行的任务的标识（方框808）并解锁共享存储器空间（方框809）。

公开(公告)号：WO1997002658A1

公开(公告)日：1997-01-23

申请号：PCT/US1996006932

申请日：1996-05-14

Applicant: INTEL CORPORATION ,  ALLEN, Michael, J.

Inventor： INTEL CORPORATION

IPC: H03K17/16

CPC classification number: H04L25/0278 ,  H03K19/018521 ,  H04L25/028

Abstract: A low power termination method and apparatus. The termination circuit (250) is typically coupled to a bus (260) through an interface node (150) to receive a rising edge of an input voltage signal. A clamping device (200, 210) is coupled to the interface node (150) and coupled to receive a clamping voltage, the clamping voltage being less than a termination voltage. The termination circuit also includes a bias supply providing a bias supply voltage. A control terminal (205, 215) of the clamping device (200, 210) is coupled to receive the bias voltage and clamps the interface node (150) when the input voltage signal exceeds a termination voltage. A bias excursion of the bias voltage may be provided responsive to the rising edge so that the clamping device clamps the interface node before the input voltage signal exceeds the termination voltage. Similarly, a second clamping device biased by a second bias supply may be used. The second clamping device clamps the interface node after the input voltage signal falls below an excursion responsive to a falling edge of the input voltage signal so that the second clamping device clamps the interface node before the input falls below the expected low voltage.

Abstract translation: 一种低功率终端方法和装置。 终端电路（250）通常通过接口节点（150）耦合到总线（260），以接收输入电压信号的上升沿。 夹紧装置（200,210）耦合到接口节点（150）并且被耦合以接收钳位电压，钳位电压小于终止电压。 终端电路还包括提供偏置电源电压的偏置电源。 当输入电压信号超过终止电压时，夹紧装置（200,210）的控制端子（205,215）被耦合以接收偏置电压并钳位接口节点（150）。 可以响应于上升沿来提供偏置电压的偏置偏移，使得钳位装置在输入电压信号超过终止电压之前钳位接口节点。 类似地，可以使用由第二偏置电源偏置的第二钳位装置。 第二钳位装置在输入电压信号下降到低于输入电压信号的下降沿的偏移之前夹紧接口节点，使得第二钳位装置在输入低于预期的低电压之前夹紧接口节点。

公开(公告)号：WO1996030819A1

公开(公告)日：1996-10-03

申请号：PCT/US1996004412

申请日：1996-03-28

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  TYMCHENKO, Viktor, A.

IPC: G06F01/08

CPC classification number: G06F1/08

Abstract: An oscillator output selector (26) and complementary control circuitry (28) are provided to a computer system. The oscillator output selector (26) is used to select a series of clock pulses for usage as a system bus clock. The control circuitry (28) controls the selection being made by the oscillator output selector, in accordance to control inputs received. In one embodiment, the control circuitry receives system bus clock frequency preferences from the CPU boards (12a-12b) as control inputs, and in response, the control circuitry causes the oscillator output selector to select the series of clock pulses having a frequency that is equal to or slower than the slowest preferred frequency. In an alternate embodiment, the control circuitry receives CPU types from the CPU boards as control inputs, and in response, the control circuitry causes the oscillator output selector to select a series of clock pulses having a frequency that will allow maximum total CPU clock frequency utilization.

Abstract translation: 振荡器输出选择器（26）和互补控制电路（28）被提供给计算机系统。 振荡器输出选择器（26）用于选择一系列用作系统总线时钟的时钟脉冲。 控制电路（28）根据接收到的控制输入来控制由振荡器输出选择器进行的选择。 在一个实施例中，控制电路从作为控制输入的CPU板（12a-12b）接收系统总线时钟频率偏好，并且作为响应，控制电路使得振荡器输出选择器选择频率为 等于或慢于最慢的优选频率。 在替代实施例中，控制电路从CPU板接收CPU类型作为控制输入，并且作为响应，控制电路使振荡器输出选择器选择一系列时钟脉冲，该时钟脉冲具有允许最大总CPU时钟频率利用率 。

公开(公告)号：WO1996026479A1

公开(公告)日：1996-08-29

申请号：PCT/US1996001294

申请日：1996-02-02

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  GEE, Homer, T. ,  STEERE, Daniel C., Jr. ,  MATTHEWS, Walter, S.

IPC: G06F01/16

CPC classification number: H05K5/0269

Abstract: A modular PCMCIA card comprises a base member (10) conforming to the Type I or Type II physical dimensions and an add on section which mechanically and electrically connects through pins (26) and sockets (28) with the base member and has dimensions such that when the base member and the add on section are joined, they conform to the dimensions of a PCMCIA Type III card. The add on section may contain one or more functional units of a stand alone computer system and may contain a battery, a modem, pager and/or an infrared transceiver for communicating with printers, computers or controlling devices.

Abstract translation: 模块化PCMCIA卡包括符合I型或II型物理尺寸的基座构件（10）和通过销（26）和插座（28）与基座构件机械地和电连接的附加部分，并具有如下尺寸： 当基座和附加部分连接时，它们符合PCMCIA III型卡的尺寸。 附加部分可以包含独立计算机系统的一个或多个功能单元，并且可以包含用于与打印机，计算机或控制设备通信的电池，调制解调器，寻呼机和/或红外收发器。