公开(公告)号：US20180323367A1

公开(公告)日：2018-11-08

申请号：US15735613

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Kevin P. O'Brien ,  David L. Kencke ,  Elijah V. Karpov ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau ,  Niloy Mukherjee ,  Prashant Majhi

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L45/00

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

Abstract: An embodiment includes an apparatus comprising: first and second electrodes on a substrate; a perpendicular magnetic tunnel junction (pMTJ), between the first and second electrodes, comprising a dielectric layer between a fixed layer and a free layer; and an additional dielectric layer directly contacting first and second metal layers; wherein (a) the first metal layer includes an active metal and the second metal includes an inert metal, and (b) the second metal layer directly contacts the free layer. Other embodiments are described herein.

公开(公告)号：US20180240970A1

公开(公告)日：2018-08-23

申请号：US15755437

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/12 ,  H01F10/32 ,  H01F41/30 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01F10/3272 ,  H01F10/3286 ,  H01F41/307 ,  H01L43/08 ,  H01L43/10

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.

公开(公告)号：US20240113220A1

公开(公告)日：2024-04-04

申请号：US17958094

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Uygar E. Avci ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Jason C. Retasket ,  Shriram Shivaraman ,  Dominique A. Adams ,  Carly Rogan ,  Punyashloka Debashis ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Sudarat Lee

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

CPC classification number: H01L29/78391 ,  H01L21/0254 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7606

Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

公开(公告)号：US20240113212A1

公开(公告)日：2024-04-04

申请号：US17956296

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Hai Li ,  Arnab Sen Gupta ,  Gauri Auluck ,  I-Cheng Tung ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Punyashloka Debashis

IPC: H01L29/775 ,  H01L21/02 ,  H01L21/465 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/465 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.

公开(公告)号：US20240097031A1

公开(公告)日：2024-03-21

申请号：US17947071

申请日：2022-09-16

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Rachel A. Steinhardt ,  Brandon Holybee ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Ian Alexander Young ,  Raseong Kim ,  Carly Rogan ,  Dominique A. Adams ,  Arnab Sen Gupta ,  Marko Radosavljevic ,  Scott B. Clendenning ,  Gauri Auluck ,  Hai Li ,  Matthew V. Metz ,  Tristan A. Tronic ,  I-Cheng Tung

IPC: H01L29/78 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L29/516

Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

公开(公告)号：US20230411390A1

公开(公告)日：2023-12-21

申请号：US17842462

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Ande Kitamura ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Kirby Maxey ,  Rachel A. Steinhardt ,  Scott B. Clendenning ,  Sudarat Lee ,  Uygar E. Avci ,  Chelsey Dorow

IPC: H01L27/092 ,  H03K19/0185 ,  H01L29/26 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L27/092 ,  H03K19/018571 ,  H01L29/26 ,  H01L23/5226 ,  H01L23/53295 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/5283

Abstract: In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC).

公开(公告)号：US20230197836A1

公开(公告)日：2023-06-22

申请号：US17557128

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Carl Hugo Naylor ,  Christopher J. Jezewski ,  Jeffery D. Bielefeld ,  Jiun-Ruey Chen ,  Ramanan V. CHEBIAM ,  Mauro J. Kobrinsky ,  Matthew V. Metz ,  Scott B. Clendenning ,  Sudurat Lee ,  Kevin P. O'Brien ,  Kirby Kurtis Maxey ,  Ashish Verma Penumatcha ,  Chelsey Jane Dorow ,  Uygar E. Avci

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7606 ,  H01L29/0665 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02568 ,  H01L29/401 ,  H01L29/66969

Abstract: Described herein are integrated circuit devices with conductive regions formed from MX or MAX materials. MAX materials are layered, hexagonal carbides and nitrides that include an early transition metal (M) and an A group element (A). MX materials remove the A group element. MAX and MX materials are highly conductive, and their two-dimensional layer structure allows very thin layers to be formed. MAX or MX materials can be used to form several conductive elements of IC circuits, including contacts, interconnects, or liners or barrier regions for contacts or interconnects.

公开(公告)号：US20230091766A1

公开(公告)日：2023-03-23

申请号：US17483651

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Ved V. Gund ,  Kevin P. O'Brien ,  Kimin Jun ,  Edris Mohammed ,  Arnab Sen Gupta ,  Matthew V. Metz ,  Ibrahim L. Ban ,  Paul Fischer

IPC: H03H9/54 ,  H03H9/17 ,  H03H9/13 ,  H04B1/16

Abstract: In one embodiment, a resonator device includes a substrate comprising a piezoelectric material and a set of electrodes on the substrate. The electrodes are in parallel and a width of the electrodes is equal to a distance between the electrodes. The resonator device further includes a set of switches, with each switch coupled to a respective electrode. The switches are to connect to opposite terminals of an alternating current (AC) signal source and select between the terminals of the AC signal source based on an input signal.

公开(公告)号：US20220102499A1

公开(公告)日：2022-03-31

申请号：US17032989

申请日：2020-09-25

Applicant: INTEL CORPORATION

Inventor： Carl Hugo Naylor ,  Kevin P. O'Brien ,  Chelsey Jane Dorow ,  Kirby Kurtis Maxey ,  Tanay Arun Gosavi ,  Ashish Verma Penumatcha ,  Urusa Shahriar Alaan ,  Uygar E. Avci

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/08 ,  H01L29/24

Abstract: Disclosed herein are transistors including two-dimensional materials, as well as related methods and devices. In some embodiments, a transistor may include a first two-dimensional channel material and a second two-dimensional source/drain (S/D) material in a source/drain (S/D), and the first two-dimensional material and the second two-dimensional material may have different compositions or thicknesses. In some embodiments, a transistor may include a first two-dimensional material in a channel and a second two-dimensional material in a source/drain (S/D), wherein the first two-dimensional material is a single-crystal material, and the second two-dimensional material is a single-crystal material.

公开(公告)号：US20210408288A1

公开(公告)日：2021-12-30

申请号：US16913835

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl NAYLOR ,  Chelsey DOROW ,  Kirby MAXEY ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Chia-Ching LIN ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.