公开(公告)号：US20220129399A1

公开(公告)日：2022-04-28

申请号：US17431739

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Kun Tian ,  Yan Zhao ,  Yu Zhang

IPC: G06F13/28

Abstract: Systems, apparatuses and methods may provide for a frontend driver that notifies a hypervisor of a map request from a guest driver of a device, wherein the device is passed through to and directly controlled by a virtual machine, and wherein the map request is associated with an attempt of the device to access a guest memory page in a virtualized execution environment. The frontend driver may also determine whether the guest memory page is pinned and send a map hypercall to the hypervisor if the guest memory page is not pinned. Additionally, the hypervisor may determine that the guest memory page is pinned, determine, based on a direct memory access (DMA) bitmap, that an unmap request from the guest driver has been issued, and unpin the guest memory page.

公开(公告)号：US11200183B2

公开(公告)日：2021-12-14

申请号：US16493148

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  Utkarsh Y. Kakaiya ,  Kun Tian

IPC: G06F13/28 ,  G06F13/24 ,  G06F9/455 ,  G06F9/48

Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.

公开(公告)号：US11099880B2

公开(公告)日：2021-08-24

申请号：US16481441

申请日：2017-02-22

Applicant: INTEL CORPORATION

Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Philip R. Lantz ,  Jason W. Brandt ,  Vedvyas Shanbhogue ,  Utkarsh Y. Kakaiya ,  Kun Tian

IPC: G06F9/455 ,  G06F12/1045 ,  G06F12/109 ,  G06F9/30

Abstract: A processing device comprises an address translation circuit to intercept a work request from an I/O device. The work request comprises a first ASID to map to a work queue. A second ASID of a host is allocated for the first ASID based on the work queue. The second ASID is allocated to at least one of: an ASID register for a dedicated work queue (DWQ) or an ASID translation table for a shared work queue (SWQ). Responsive to receiving a work submission from the SVM client to the I/O device, the first ASID of the application container is translated to the second ASID of the host machine for submission to the I/O device using at least one of: the ASID register for the DWQ or the ASID translation table for the SWQ based on the work queue associated with the I/O device.

公开(公告)号：US11055147B2

公开(公告)日：2021-07-06

申请号：US16351396

申请日：2019-03-12

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  Sanjay Kumar ,  Kun Tian ,  Philip Lantz

IPC: G06F9/50 ,  H04L12/58 ,  G06F15/76 ,  G06F15/17 ,  H04L29/08 ,  H04L29/12

Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

公开(公告)号：US10970129B2

公开(公告)日：2021-04-06

申请号：US16156550

申请日：2018-10-10

Applicant: Intel Corporation

Inventor： Kun Tian ,  Zhiyuan Lv ,  Yao Zu Dong

IPC: G06F9/52 ,  G06F9/48 ,  G06F9/455 ,  G06T1/20 ,  G06F9/50

Abstract: Technologies for scheduling workload submissions for a graphics processing unit (GPU) in a virtualization environment include a GPU scheduler embodied in a computing device. The virtualization environment includes a number of different virtual machines that are configured with a native graphics driver. The GPU scheduler receives GPU commands from the different virtual machines, dynamically selects a scheduling policy, and schedules the GPU commands for processing by the GPU.

公开(公告)号：US20200294183A1

公开(公告)日：2020-09-17

申请号：US16791904

申请日：2020-02-14

Applicant: Intel Corporation

Inventor： Kun Tian ,  Yao Zu Dong ,  Zhiuyuan LV

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06T1/60

Abstract: Systems and methods for container access to graphics processing unit (GPU) resources are disclosed herein. In some embodiments, a computing system may include a physical GPU and kernel-mode driver circuitry, to communicatively couple with the physical GPU to create a plurality of emulated GPUs and a corresponding plurality of device nodes. Each device node may be associated with a single corresponding user-side container to enable communication between the user-side container and the corresponding emulated GPU. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US10580108B2

公开(公告)日：2020-03-03

申请号：US16062511

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Yao Zu Dong ,  Kun Tian ,  Tian Zhang ,  Yulei Zhang

IPC: G06T1/20 ,  G06F9/48

Abstract: An apparatus and method for best effort quality of service scheduling in a graphics processing architecture. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) to perform graphics processing operations for a plurality of guests; a plurality of buffers to store one or more graphics commands associated with each guest to be executed by the GPU; and a scheduler to evaluate commands in the buffers of a first guest to estimate a cost of executing the commands, the scheduler to select all or a subset of the buffers of the first guest for execution on the GPU based on a determination that the selected buffers can be executed by the GPU within a remaining time slice allocated to the first guest.

公开(公告)号：US10228981B2

公开(公告)日：2019-03-12

申请号：US15584979

申请日：2017-05-02

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  Sanjay Kumar ,  Kun Tian ,  Philip Lantz

IPC: G06F3/06 ,  G06F9/50 ,  H04L29/08 ,  H04L12/24 ,  H04L12/58 ,  H04L29/12 ,  G06F15/17

Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

公开(公告)号：US20180307533A1

公开(公告)日：2018-10-25

申请号：US15493698

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Kun Tian ,  David J. Cowperthwaite ,  Murali Ramadoss ,  Balaji Vembu ,  Zhi Wang ,  Eric C. Samson ,  Altug Koker ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06F9/48 ,  G06T1/20

CPC classification number: G06F9/4887 ,  G06F9/4831 ,  G06T1/20 ,  G06T1/60 ,  G06T2210/52

Abstract: A mechanism is described for facilitating multi-level scheduling of workloads in computing devices. A method of embodiments, as described herein, includes facilitating multiple levels of scheduling for processing of workloads using multiple levels of queues, where the workloads are associated with a device including a processor of a computing device.

公开(公告)号：US20170329623A1

公开(公告)日：2017-11-16

申请号：US15529426

申请日：2014-11-24

Applicant: INTEL CORPORATION

Inventor： Yaozu Dong ,  Kun Tian

IPC: G06F9/455 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06F9/45558 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06T1/20 ,  G06T1/60

Abstract: Methods, software, and apparatus for application transparent, high available GPU computing with VM checkpointing. The guest access of certain GPU resources, such as MMIO resources, are trapped to keep a copy of guest context per semantics, and/or emulate the guest access of the resources prior to submission to the GPU, while other commands relating to certain graphics memory address regions are trapped before being passed through to the GPU. The trapped commands are scanned before submission to predict: a) potential to-be-dirtied graphics memory pages, and b) the execution time of intercepted commands, so the next checkpointing can be aligned to a predicted execution time. The GPU internal states are drained by flushing internal context/tlb/cache, at the completion of submitted commands, and then a snapshot of the vGPU state is taken, based on tracked GPU state, GPU context (through GPU-specific commands), detected dirty graphics memory pages and predicted to-be dirtied graphics memory pages.