公开(公告)号：US20240338319A1

公开(公告)日：2024-10-10

申请号：US18745603

申请日：2024-06-17

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  Ashok Raj ,  Kun Tian

IPC: G06F12/1009 ,  G06F9/455 ,  G06F12/06 ,  G06F12/1081

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F12/063 ,  G06F12/1081 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45591

Abstract: Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.

公开(公告)号：US12045185B2

公开(公告)日：2024-07-23

申请号：US18296875

申请日：2023-04-06

Applicant: Intel Corporation

Inventor： Philip R. Lantz ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Saurabh Gayen

IPC: G06F13/364 ,  G06F9/50 ,  G06F13/24

CPC classification number: G06F13/364 ,  G06F9/5027 ,  G06F13/24

Abstract: Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

公开(公告)号：US20240232096A9

公开(公告)日：2024-07-11

申请号：US18279029

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Phillip Lantz ,  Rajesh Sankaran ,  David Hansen ,  Evgeny V. Voevodin ,  Andrew Anderson ,  Lizhen You ,  Xin Zhou ,  Nikhil Talpallikar

IPC: G06F12/1009

CPC classification number: G06F12/1009

Abstract: An embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. Other embodiments are disclosed and claimed.

公开(公告)号：US11656899B2

公开(公告)日：2023-05-23

申请号：US17404897

申请日：2021-08-17

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Philip R. Lantz ,  Jason W. Brandt ,  Vedvyas Shanbhogue ,  Utkarsh Y. Kakaiya ,  Kun Tian

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1045 ,  G06F12/109

CPC classification number: G06F9/45558 ,  G06F9/30138 ,  G06F12/109 ,  G06F12/1063 ,  G06F2009/45579 ,  G06F2212/152

Abstract: Implementations of the disclosure provide a processing device comprising an address translation circuit to intercept a work request from an I/O device. The work request comprises a first ASID to map to a work queue. A second ASID of a host is allocated for the first ASID based on the work queue. The second ASID is allocated to at least one of: an ASID register for a dedicated work queue (DWQ) or an ASID translation table for a shared work queue (SWQ). Responsive to receiving a work submission from the SVM client to the I/O device, the first ASID of the application container is translated to the second ASID of the host machine for submission to the I/O device using at least one of: the ASID register for the DWQ or the ASID translation table for the SWQ based on the work queue associated with the I/O device.

公开(公告)号：US20230134657A1

公开(公告)日：2023-05-04

申请号：US17519384

申请日：2021-11-04

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Philip R. Lantz ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Rupin H. Vakharwala

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/54 ,  G06F13/24

Abstract: A system comprises a physical processor to execute a virtual machine manager to run, on a logical core, a virtual machine including a guest user application and a virtual CPU. Circuitry coupled to an external device is to receive an interrupt request from the external device for the guest user application, locate a first interrupt data structure associated with the guest user application, generate a first interrupt with the first interrupt data structure based on a first interrupt vector for the interrupt request, locate a second interrupt data structure associated with the virtual CPU, and generate a first notification interrupt for the virtual CPU with the second interrupt data structure based on a first notification vector in the first interrupt data structure. The circuitry may generate a second notification interrupt for the logical core using a second notification vector and a logical core identifier from the second interrupt data structure.

公开(公告)号：US20230093247A1

公开(公告)日：2023-03-23

申请号：US17481770

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Bhargavi Narayanasetty ,  Andrew Anderson ,  Anupama Kurpad ,  Evgeny V. Voevodin ,  Patrick Ndouniama ,  Sai Prashanth Muralidhara ,  Rajat Agarwal ,  Mohamed Arafa

IPC: G06F3/06

Abstract: An embodiment of an integrated circuit may comprise local memory, a plurality of per-page counters located in a non-system-addressable region of the local memory, and circuitry coupled to the local memory, the circuitry to count accesses to pages of a system-addressable memory space with the plurality of per-page counters located in the non-system-addressable region of the local memory. Other embodiments are disclosed and claimed.

公开(公告)号：US20230032586A1

公开(公告)日：2023-02-02

申请号：US17711928

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Narayan Ranganathan ,  Philip R. Lantz ,  Rajesh M. Sankaran ,  Sanjay Kumar ,  Saurabh Gayen ,  Nikhil Rao ,  Utkarsh Y. Kakaiya ,  Dhananjay A. Joshi ,  David Jiang ,  Ashok Raj

IPC: G06F3/06 ,  G06F9/455

Abstract: Methods and apparatus relating to scalable access control checking for cross-address-space data movement are described. In an embodiment, a memory stores an InterDomain Permissions Table (IDPT) having a plurality of entries. At least one entry of the IDPT provides a relationship between a target address space identifier and a plurality of requester address space identifiers. A hardware accelerator device allows access to a target address space, corresponding to the target address space identifier, by one or more of requesters, corresponding to the plurality of requester address space identifiers, respectively, based at least in part on the relationship provided by the at least one entry of the IDPT. Other embodiments are also disclosed and claimed.

公开(公告)号：US11461100B2

公开(公告)日：2022-10-04

申请号：US17253053

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Kun Tian ,  Sanjay Kumar ,  Ashok Raj ,  Yi Liu ,  Rajesh M. Sankaran ,  Philip R. Lantz

IPC: G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F12/1009 ,  G06F13/42

Abstract: Process address space identifier virtualization uses hardware paging hint. The processing device (100) comprising: a processing core (110); and a translation circuit coupled to the processing core, the translation circuit to: receive a workload instruction from a guest application being executed by the processing device, the workload instruction comprising an untranslated guest process address space identifier (gPASID), a workload for an input/output (I/O) target device, and an identifier of a submission register on the I/O target device (410), access a paging data structure (PDS) associated with the guest application to retrieve a page table entry corresponding to the gPASID and the identifier of the submission register (420), determine a value of an I/O hint bit of the page table entry corresponding to the gPASID and the identifier of the submission register (430), responsive to determining that the I/O hint bit is enabled, keep the untranslated gPASID in the workload instruction (440), and provide the workload instruction to a work queue of the I/O target device (450).

公开(公告)号：US20210173790A1

公开(公告)日：2021-06-10

申请号：US16651786

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  Ashok Raj ,  Kun Tian

IPC: G06F12/1009 ,  G06F12/1081 ,  G06F12/06 ,  G06F9/455

Abstract: Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.

公开(公告)号：US20210064525A1

公开(公告)日：2021-03-04

申请号：US16958479

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Kun Tian ,  Rajesh Sankaran ,  Sanjay Kumar ,  Ashok Raj

IPC: G06F12/06 ,  G06F12/1081 ,  G06F12/1036 ,  G06F12/0891 ,  G06F9/455

Abstract: A processor includes a hardware input/output (I/O) memory management unit (IOMMU) and a core, which executes an instruction to intercept a payload from a virtual machine (VM). The payload contains a guest bus device function (BDF) identifier, a guest address space identifier (ASID), and a guest address range. The core accesses, within a virtual machine control structure stored in memory, pointers to a first set of translation tables and a second set of translation tables. The core traverses the first set of translation tables to translate the guest BDF identifier to a host BDF identifier and traverses the second set of translation tables to translate the guest ASID to a host ASID. The core stores the host BDF identifier and the host ASID in the payload and submits, to the hardware IOMMU, an administrative command containing the payload to perform invalidation of the guest address range.