公开(公告)号：US10516104B2

公开(公告)日：2019-12-24

申请号：US15755571

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Elijah V. Karpov ,  Uday Shah ,  Ravi Pillarisetty ,  Niloy Mukherjee

IPC: G11C13/00 ,  H01L45/00

Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; a first oxide layer between the OEL and the bottom electrode; and a second oxide layer between the first oxide layer and the bottom electrode; wherein (a) a first plurality of oxygen vacancies are within the first oxide layer and are adjacent the OEL at a first concentration, (b) a second plurality of oxygen vacancies are within the first oxide layer and are adjacent the second oxide layer at a second concentration that is less than the first concentration, and (c) the first oxide layer includes a first oxide material different from a second oxide material included in the second oxide layer. Other embodiments are described herein.

公开(公告)号：US20190333906A1

公开(公告)日：2019-10-31

申请号：US16475085

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Anup Pancholi ,  Prashant Majhi ,  Paul B. Fischer ,  Patrick Morrow

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; a second active device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first set and the second active device, wherein the layer is to bond the one of the layers of the first set and the second active device.

公开(公告)号：US20190333839A1

公开(公告)日：2019-10-31

申请号：US15966577

申请日：2018-04-30

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Elijah V. Karpov ,  Prashant Majhi ,  Brian S. Doyle

IPC: H01L23/38 ,  H01L23/34 ,  H01L27/16 ,  H01L27/24 ,  H01L27/22 ,  H01L35/30 ,  H01L35/16 ,  H01L35/18 ,  H01L43/02 ,  H01L45/00

Abstract: Electronic devices, memory devices, and computing devices are disclosed. An electronic device includes electronic circuitry, a temperature sensor, a heat sink, at least one thermoelectric material, a thermally conductive material configured to thermally couple the electronic circuitry to the at least one thermoelectric material, and a transistor. The temperature sensor is configured to monitor a temperature of the electronic circuitry. The transistor is configured to selectively enable thermoelectric current to flow through the at least one thermoelectric material and dissipate heat from the thermally conductive material to the heat sink responsive to fluctuations in the temperature of the electronic circuitry detected by the temperature sensor.

公开(公告)号：US10388869B2

公开(公告)日：2019-08-20

申请号：US15505905

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Elijah V. Karpov ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Robert S. Chau

IPC: H01L45/00

Abstract: Thin film resistive memory material stacks including at least one of a high work function metal oxide at an interface of a first electrode and a thin film memory material, and a low work function rare earth metal at an interface of a second electrode and the thin film memory material. The high work function metal oxide provides a good Schottky barrier height relative to memory material for high on/off current ratio. Compatibility of the metal oxide with switching oxide reduces cycling loss of oxygen/vacancies for improved memory device durability. The low work function rare earth metal provides high oxygen solubility to enhance vacancy creation within the memory material in as-deposited state for low forming voltage requirements while providing an ohmic contact to the resistive memory material.

公开(公告)号：US10355112B2

公开(公告)日：2019-07-16

申请号：US15719776

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/778

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

公开(公告)号：US20190214433A1

公开(公告)日：2019-07-11

申请号：US16315340

申请日：2016-09-24

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Prashant Majhi ,  Ravi Pillarisetty ,  Niloy Mukherjee

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: Disclosed herein are asymmetric selectors for memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a storage element; and a selector device coupled to the storage element, wherein the selector device has a positive threshold voltage and a negative threshold voltage, and a magnitude of the positive threshold voltage is different from a magnitude of the negative threshold voltage.

公开(公告)号：US10340275B2

公开(公告)日：2019-07-02

申请号：US15574092

申请日：2015-06-23

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Jack T. Kavalieros ,  Robert S. Chau ,  Niloy Mukherjee ,  Rafael Rios ,  Prashant Majhi ,  Van H. Le ,  Ravi Pillarisetty ,  Uday Shah ,  Gilbert Dewey ,  Marko Radosavljevic

IPC: H01L27/12 ,  H01L27/108 ,  H01L27/24 ,  G11C13/00 ,  H01L27/11551 ,  H01L27/1156 ,  H01L29/786 ,  H01L45/00

Abstract: A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a first memory cell. A second memory cell is over the first memory. A logic block is coupled to at least the first memory cell.

公开(公告)号：US10090461B2

公开(公告)日：2018-10-02

申请号：US15126138

申请日：2014-06-26

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Prashant Majhi ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Niloy Mukherjee ,  Uday Shah ,  Robert S. Chau

IPC: H01L47/00 ,  H01L45/00

Abstract: Oxide-based three-terminal resistive switching logic devices and methods of fabricating oxide-based three-terminal resistive switching logic devices are described. In a first example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes an active oxide material region disposed directly between a metal source region and a metal drain region. The device also includes a gate electrode disposed above the active oxide material region. In a second example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes a first active oxide material region spaced apart from a second oxide material region. The device also includes metal input regions disposed on either side of the first and second active oxide material regions. A metal output region is disposed between the first and second active oxide material regions.

公开(公告)号：US09859278B2

公开(公告)日：2018-01-02

申请号：US15037618

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Robert S. Chau

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/423 ,  H01L29/786 ,  H01L29/267

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/78669 ,  H01L29/78684

Abstract: An apparatus including a complimentary metal oxide semiconductor (CMOS) inverter including an n-channel metal oxide semiconductor field effect transistor (MOSFET); and a p-channel MOSFET, wherein a material of a channel in the n-channel MOSFET and a material of a channel in the p-channel MOSFET is subject to a bi-axial tensile strain. A method including forming an n-channel metal oxide semiconductor field effect transistor (MOSFET); forming a p-channel MOSFET; and connecting the gate electrodes and the drain regions of the n-channel MOSFET and the p-channel MOSFET, wherein a material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET is subject to a bi-axial tensile strain.

公开(公告)号：US09806180B2

公开(公告)日：2017-10-31

申请号：US14558947

申请日：2014-12-03

Applicant: Intel Corporation

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/778

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.