公开(公告)号：US11948831B2

公开(公告)日：2024-04-02

申请号：US17322742

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： Anup Pancholi ,  Prashant Majhi ,  Paul Fischer ,  Patrick Morrow

IPC: H01L21/762 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L21/76251 ,  H01L23/5226 ,  H01L24/06 ,  H01L24/17

Abstract: An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

公开(公告)号：US20240006381A1

公开(公告)日：2024-01-04

申请号：US17854728

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Stephen Morein ,  Ravindranath Vithal Mahajan ,  Prashant Majhi

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06548

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of vertically stacked dies; a trench of dielectric material through the plurality of vertically stacked dies; and a plurality of conductive vias extending through the trench of dielectric material, wherein individual ones of the plurality of conductive vias are electrically coupled to individual ones of the plurality of vertically stacked dies.

公开(公告)号：US20240006366A1

公开(公告)日：2024-01-04

申请号：US17854613

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Stephen Morein ,  Ravindranath Vithal Mahajan ,  Prashant Majhi

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/24 ,  H01L2224/2405 ,  H01L24/20 ,  H01L2924/37001 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1431 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2924/15331 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/215 ,  H01L2224/24145 ,  H01L2224/24011 ,  H01L25/0652

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of dies stacked vertically; a trench of dielectric material extending through the plurality of dies; a conductive via extending through the trench of dielectric material; and a plurality of conductive pathways between the plurality of dies and the conductive via, wherein individual ones of the conductive pathways are electrically coupled to the conductive via and to individual ones of the plurality of dies, and wherein the individual ones of the plurality of conductive pathways have a first portion including a first material and a second portion including a second material different from the first material.

公开(公告)号：US20230223475A1

公开(公告)日：2023-07-13

申请号：US18174825

申请日：2023-02-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  Prashant Majhi ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/6684

Abstract: Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.

公开(公告)号：US20230197825A1

公开(公告)日：2023-06-22

申请号：US17555247

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Anand Murthy

IPC: H01L29/45

CPC classification number: H01L29/456 ,  H01L29/7851

Abstract: Transition metal dichalcogenide (TMD) monolayers are positioned between a contact metal and a semiconductor to pin the Fermi level at the metal-semiconductor interface. The pinned Fermi level can provide for a lower Schottky barrier height between the contact metal and semiconductor than if no TMD were present at the contact metal-semiconductor interface. The height of the Schottky barrier can be tuned through the selection of the transition metal dichalcogenide used for the monolayer. Transition metal dichalcogenides have the chemical formula MX2, where M is a transition metal and X=sulfur, selenium, or tellurium. The transition metal dichalcogenides used for metal contact-semiconductor interfaces can have M=titanium, platinum, molybdenum, tungsten, erbium, rhodium, or lanthanum. A lower Schottky barrier height can reduce contact resistance, which can improve transistor performance as the parasitic resistance of source/drain channels approach that of transistor channel as transistor geometries continued to scale.

公开(公告)号：US20230197568A1

公开(公告)日：2023-06-22

申请号：US17556520

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Anand Murthy

IPC: H01L23/48 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L23/49838 ,  H01L23/49827 ,  H01L28/75 ,  H01L28/92 ,  H01L21/486 ,  H01L21/76898 ,  H01L25/0655

Abstract: An apparatus includes a first layer comprising silicon, and a conductive feature extending within the silicon of the first layer. The conductive feature includes (i) conductive material extending throughout the length of the conductive feature, (ii) a barrier layer between the conductive material and the silicon of the first layer, and (iii) a second layer including dielectric material between the barrier layer and the silicon of the first layer. In an example, one or more discontinuous monolayers of metal are between sections of the dielectric material and the silicon of the first layer. The conductive feature is formed in a recess extending within the silicon of the first layer. In an example, the recess is formed using a metal assisted etch process using the metal as a catalyst, and one or more discontinuous monolayers of the metal are remnants of the metal used in the metal assisted etch process.

公开(公告)号：US11659722B2

公开(公告)日：2023-05-23

申请号：US16226209

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Prashant Majhi ,  Ravi Pillarisetty ,  Elijah Karpov ,  Brian Doyle ,  Anup Pancholi ,  Abhishek Sharma

IPC: H10K19/20 ,  H01L27/12 ,  H01L27/28 ,  H01L29/66 ,  H01L29/786 ,  H01L51/05 ,  H01L51/10

CPC classification number: H01L27/286 ,  H01L27/124 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/283 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0558 ,  H01L51/102

Abstract: Embodiments herein describe techniques for a semiconductor device including a semiconductor substrate, a first device of a first wafer, and a second device at back end of a second wafer, where the first device is bonded with the second device. A first metal electrode of the first device within a first dielectric layer is coupled to an n-type oxide TFT having a channel layer that includes an oxide semiconductor material. A second metal electrode of the second device within a second dielectric layer is coupled to p-type organic TFT having a channel layer that includes an organic material. The first dielectric layer is bonded to the second dielectric layer, and the first metal electrode is bonded to the second metal electrode. The n-type oxide TFT and the p-type organic TFT form a symmetrical pair of transistors of a CMOS circuit. Other embodiments may be described and/or claimed.

公开(公告)号：US11640839B2

公开(公告)日：2023-05-02

申请号：US17570249

申请日：2022-01-06

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Elijah V. Karpov

IPC: G11C11/22 ,  H01L27/11585

Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.

公开(公告)号：US11631717B2

公开(公告)日：2023-04-18

申请号：US16147068

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Charles Kuo ,  Prashant Majhi ,  Abhishek Sharma ,  Willy Rachmady

IPC: H01L27/24 ,  G11C7/18 ,  G11C8/14 ,  G11C13/00 ,  H01L45/00

Abstract: A memory cell is disclosed. The memory cell includes a storage component that includes a chalcogenide stack that includes a plurality of layers of material and a selector component that includes a Schottky diode.

公开(公告)号：US20230086977A1

公开(公告)日：2023-03-23

申请号：US17477891

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Brian S. Doyle ,  Van H. Le ,  Abhishek A. Sharma

IPC: H01L27/088 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

Abstract: Described herein are integrated circuit (IC) devices that include devices that include fin-based field-effect transistors (FinFETs) integrated over gate-all-around (GAA) transistors. The GAA transistors may serve to provide high-performance compute logic, and may be relatively low-voltage transistors, while FinFETs may be more suitable than GAA transistors for providing high-voltage transistors, and, therefore, may serve to provide peripheral logic for backend memory arrays implemented over the same support structure over which the GAA transistors and the FinFETs are provided. Such an arrangement may address the fundamental voltage incompatibility by integrating a mix of FinFETs and GAA transistors in stacked complimentary FET (CFET) architecture to enable embedded 1T-1X based memories.