公开(公告)号：US09818870B2

公开(公告)日：2017-11-14

申请号：US14914847

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack T. Kavalieros ,  Robert S. Chau ,  Benjamin Chu-Kung ,  Roza Kotlyar

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/10 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/51 ,  H01L29/165 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/7842 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/512 ,  H01L29/66439 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696

Abstract: An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first band gap less than a band gap of a material of the substrate and a second material having a second band gap that is greater than the first band gap; and a gate stack on the channel region, wherein the second material is disposed between the first material and the gate stack. A method including forming a first material having a first band gap on a substrate; forming a second material having a second band gap greater than the first band gap on the first material; and forming a gate stack on the second material.

公开(公告)号：US09478635B2

公开(公告)日：2016-10-25

申请号：US14924643

申请日：2015-10-27

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/66 ,  H01L29/267 ,  H01L21/283 ,  H01L29/15 ,  H01L21/02 ,  H01L29/165 ,  H01L29/778 ,  H01L29/775 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

公开(公告)号：US09184294B2

公开(公告)日：2015-11-10

申请号：US14494968

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Anand S. Murthy ,  Glenn A. Glass ,  Daniel B. Aubertine ,  Tahir Ghani ,  Jack T. Kavalieros ,  Roza Kotlyar

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L29/1054 ,  H01L21/76224 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

Abstract translation: 公开了用于将高迁移率应变通道结合到鳍状晶体管（例如，诸如双栅极，三相等等的FinFET）中的技术，其中应力材料被包覆到鳍的沟道区域上。 在一个示例性实施例中，硅锗（SiGe）被包覆到硅散热片上以提供期望的应力，尽管可以使用其它鳍和包层材料。 这些技术与典型的工艺流程兼容，并且包层沉积可以发生在工艺流程内的多个位置处。 在一些情况下，来自包覆层的内置应力可以通过压缩通道中的鳍和覆层的源极/漏极应力来增强。 在一些情况下，可以提供可选的封盖层以改善栅极电介质/半导体界面。 在一个这样的实施例中，硅被提供在SiGe包覆层上以改善栅极电介质/半导体界面。

公开(公告)号：US11581406B2

公开(公告)日：2023-02-14

申请号：US17453088

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Anand S. Murthy ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/161 ,  H01L27/092 ,  H01L29/778 ,  H01L29/165 ,  H01L27/12 ,  H01L29/78 ,  H01L29/04

Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

公开(公告)号：US11387320B2

公开(公告)日：2022-07-12

申请号：US16707490

申请日：2019-12-09

Applicant: INTEL CORPORATION

Inventor： Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack T. Kavalieros ,  Roza Kotlyar ,  Willy Rachmady ,  Mark Y. Liu

IPC: H01L29/06 ,  H01L21/285 ,  H01L29/165 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/768 ,  H01L29/167 ,  H01L21/02 ,  H01L29/08 ,  H01L29/36 ,  H01L27/092 ,  H01L23/535 ,  H01L29/417 ,  H01L21/3215 ,  H01L29/778

Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

公开(公告)号：US10854752B2

公开(公告)日：2020-12-01

申请号：US16214946

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Glenn A. Glass ,  Anand S. Murthy ,  Willy Rachmady ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

公开(公告)号：US20200295127A1

公开(公告)日：2020-09-17

申请号：US16351921

申请日：2019-03-13

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron D. Lilak ,  Anh Phan ,  Cheng-Ying Huang ,  Gilbert W. Dewey ,  Patrick Morrow ,  Rishabh Mehandru ,  Roza Kotlyar ,  Sean T. Ma ,  Willy Rachmady

IPC: H01L29/04 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L25/11 ,  H01L23/00 ,  H01L23/522 ,  H01L29/16 ,  H01L29/20 ,  H01L21/8238 ,  H01L29/66

Abstract: Disclosed herein are stacked transistors with different crystal orientations in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein the channel materials in at least some of the strata have different crystal orientations.

公开(公告)号：US10396211B2

公开(公告)日：2019-08-27

申请号：US15747925

申请日：2015-07-31

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Prashant Majhi ,  Roza Kotlyar ,  Niloy Mukherjee ,  Charles C. Kuo ,  Uday Shah ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L29/786 ,  H01L27/07 ,  H01L29/02 ,  H01L29/49 ,  H01L27/12 ,  H01L45/00 ,  H01L27/24

Abstract: A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.

公开(公告)号：US20190181337A1

公开(公告)日：2019-06-13

申请号：US16323602

申请日：2016-09-25

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Elijah V. Karpov ,  Roza Kotlyar ,  Prashant Majhi

IPC: H01L45/00 ,  H01L27/24

Abstract: Disclosed herein are metal filament memory devices (MFMDs), and related devices and techniques. In some embodiments, an MFMD may include: an electrode including an electrochemically active metal; an electrolyte; and a barrier material disposed between the electrode and the electrolyte, wherein the barrier material has a lower work function than the electrode.

公开(公告)号：US20190035893A1

公开(公告)日：2019-01-31

申请号：US16148621

申请日：2018-10-01

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Anand S. Murthy ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/161 ,  H01L29/778 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.