公开(公告)号：US20190266219A1

公开(公告)日：2019-08-29

申请号：US16411730

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Rajesh Sundaram ,  Richard Coulson ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F17/16 ,  G06F7/78 ,  G06F9/38 ,  G06F9/30

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

公开(公告)号：US10068636B2

公开(公告)日：2018-09-04

申请号：US15394860

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Berkin Akin ,  Shigeki Tomishima

IPC: G11C7/22 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4093 ,  G11C7/1039 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/2209 ,  G11C2207/2245

Abstract: The present disclosure relates to a dynamic random access memory (DRAM) array, which comprises a plurality of bit lines connectable, respectively, to at least two row buffers of the DRAM array. The two row buffers are respectively connectable to data input/output (I/O) lines and are configured to electrically connect the two row buffers to the bit lines and data I/O lines in a mutually exclusive manner.

公开(公告)号：US10031684B2

公开(公告)日：2018-07-24

申请号：US15788679

申请日：2017-10-19

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Kuljit S. Bains

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/10

Abstract: Examples include techniques for a write zero operation. Example techniques include forwarding a write 0 command to a memory device to cause internal activations of column select lines of one or more blocks of memory to cause bit values or contents of the one or more blocks to have or store a value of 0.

公开(公告)号：US09934827B2

公开(公告)日：2018-04-03

申请号：US14975298

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Wei Wu ,  Shigeki Tomishima ,  Shih-Lien L. Lu

IPC: G06F13/00 ,  G11C7/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G11C7/10 ,  G11C11/406

CPC classification number: G11C7/06 ,  G06F13/1678 ,  G06F13/4018 ,  G06F13/4282 ,  G11C7/1048 ,  G11C7/1072 ,  G11C11/40618 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/107

Abstract: Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.

公开(公告)号：US09934082B2

公开(公告)日：2018-04-03

申请号：US15374922

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Charles Augustine ,  Wei Wu ,  Shih Lien L. Lu

IPC: G11C7/02 ,  G06F11/07 ,  G11C13/00 ,  G11C11/16 ,  G11C29/42 ,  G11C29/52 ,  G06F3/06 ,  G06F11/10 ,  H03M13/15 ,  H03M13/37 ,  H03M13/00

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C29/42 ,  G11C29/52 ,  G11C2013/0042 ,  G11C2213/79 ,  G11C2213/82 ,  H03M13/1575 ,  H03M13/373 ,  H03M13/6502

Abstract: Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory bit-cell via access devices; a second sense amplifier coupled to the first sense amplifier and to the complementary resistive memory bit-cell via the access devices, wherein the second sense amplifier is operable to detect an error in the complementary resistive memory bit-cell.

公开(公告)号：US09922695B2

公开(公告)日：2018-03-20

申请号：US14668895

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Shih-Lien L. Lu

IPC: G11C11/40 ,  G11C5/02 ,  G11C7/08 ,  G11C7/10 ,  G11C7/22 ,  G11C7/20 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4072 ,  G11C11/4076

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/005 ,  G11C2207/105 ,  G11C2207/107

Abstract: An apparatus comprises: a source array of memory cells with associated source sense amplifiers; a destination array of memory cells with associated destination sense amplifiers; and logic to activate a source word-line (WL) to select a row of memory cells within the source array such that data in the selected row of memory cells is latched by the associated source sense amplifiers, wherein the logic to activate a destination WL to select a row of memory cells within the destination array such that data in the selected row of memory cells is latched by the associated destination sense amplifiers, and wherein the source and destination arrays of memory cells are within a same bank of a memory.

公开(公告)号：US09761297B1

公开(公告)日：2017-09-12

申请号：US15396009

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Shigeki Tomishima

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/408 ,  G11C7/10

CPC classification number: G11C11/40615 ,  G11C11/40603 ,  G11C11/40618

Abstract: Systems, apparatuses and methods may provide a way to reduce and or eliminate contention between refresh operations and read/write operations, and a larger page buffer for read/write operations for dynamic random access memory (DRAM) technology. More particularly, systems, apparatuses and methods may provide a way to improve a DRAM to perform read/write operations with section selection. Systems, apparatuses and methods may provide for including additional transfer gates in a DRAM to provide section selection to reduce and or eliminate contention between refresh operations and read/write operations, and a larger page buffer for read/write operations.

公开(公告)号：US20170255406A1

公开(公告)日：2017-09-07

申请号：US15277182

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Kuljit S. Bains

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/068 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C16/20

Abstract: Examples include techniques for a write zero operation. Example techniques include forwarding a write 0 command to a memory device to cause internal activations of column select lines of one or more blocks of memory to cause bit values or contents of the one or more blocks to have or store a value of 0.

公开(公告)号：US09747967B2

公开(公告)日：2017-08-29

申请号：US14499067

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Helia Naeimi ,  Shih-Lien L. Lu ,  Shigeki Tomishima

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673

Abstract: In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to assist in the changing of states of bitcells of the subarray from a first state to a second state in which the ferromagnetic device of the bitcell is changed from one of parallel and anti-parallel polarization to the other of parallel and anti-parallel polarization. Accordingly, the content of the subarray may be readily preset or erased to one of the parallel or anti-parallel state with assistance from an electro-magnet. During a normal write operation, the bits to the other state are written. Other aspects are described herein.

公开(公告)号：US20170103801A1

公开(公告)日：2017-04-13

申请号：US15389223

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Shih-Lien Lu ,  Helia Naeimi ,  Shigeki Tomishima

IPC: G11C11/4094 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C11/4094 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4078 ,  G11C11/4096

Abstract: Embodiments include apparatuses, methods, and systems including a circuit which may increase a speed of removal of data stored in a memory cell. In embodiments, the circuit may include a control logic to detect a signal and a boost circuit coupled to the control logic to allow the control logic to disable an operation of the boost circuit in response to detection of the signal. A discharge device may be coupled to the boost circuit to accelerate leakage of a leakage current in response to the detection of the signal. In the embodiment, the leakage current is a leakage current of a memory cell coupled to the discharge device and acceleration of the leakage of the leakage current and the disablement of the operation of the boost circuit may increase a speed of erasure of data in the memory cell. Other embodiments may also be described and claimed.