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公开(公告)号：US10558254B2
公开(公告)日：2020-02-11
申请号：US15477042
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Altug Koker , Eric J. Hoekstra , Kiran C. Veernapu , Prasoonkumar Surti , Vasanth Ranganathan , Kamal Sinha , Balaji Vembu , Eric J. Asperheim , Sanjeev S. Jahagirdar , Joydeep Ray
IPC: G06F3/06 , G06F1/3225 , G06F1/3234
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20200042417A1
公开(公告)日：2020-02-06
申请号：US16526069
申请日：2019-07-30
Applicant: Intel Corporation
Inventor： Nikos Kaburlasos , Balaji Vembu , Josh B. Mastronarde , Altug Koker , Eric C. Samson , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Vasanth Ranganathan , Sanjeev S. Jahagirdar
IPC: G06F11/30 , G06F1/324 , G06F1/3206 , G06F1/3296 , G05F1/10 , G05F1/571 , G06F11/32 , G06F11/34
Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10453427B2
公开(公告)日：2019-10-22
申请号：US15477030
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan Bhairavabhatla , Arthur D. Hunter, Jr. , Wei-Yu Chen , Subramaniam M. Maiyuran
IPC: G09G5/36 , G06F9/46 , G06F12/0875 , G09G5/00 , G06F12/084 , G06F12/0811
Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.
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公开(公告)号：US10452586B2
公开(公告)日：2019-10-22
申请号：US15488929
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kiran C Veernapu , Balaji Vembu , Vasanth Ranganathan , Prasoonkumar Surti
IPC: G06F13/40 , G06F12/0846 , G06F9/54 , G06F13/42 , G06T1/60 , G06F12/0811 , G06F12/084 , G06F12/0831
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to monitor a thread switching overhead parameter for an application executing in a processing system and in response to a determination that the thread switching overhead parameter exceeds a threshold, to activate a thread management algorithm to reduce thread switching in the processing system. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10304154B2
公开(公告)日：2019-05-28
申请号：US15495054
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Altug Koker , John C. Weast , Mike B. Macpherson , Linda L. Hurd , Sara S. Baghsorkhi , Justin E. Gottschlich , Prasoonkumar Surti , Chandrasekaran Sakthivel , Liwei Ma , Elmoustapha Ould-Ahmed-Vall , Kamal Sinha , Joydeep Ray , Balaji Vembu , Sanjeev Jahagirdar , Vasanth Ranganathan , Dukhwan Kim
Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.
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Patent Agency Ranking
公开(公告)号：US10303953B2
公开(公告)日：2019-05-28
申请号：US15488555
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Mayuresh M. Varerkar , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Sherine Abdelhak , Sachin Godse , Farshad Akhbari , Narayan Srinivasa , Altug Koker , Nadathur Rajagopalan Satish , Dukhwan Kim , Feng Chen , Abhishek R. Appu , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman , Vasanth Ranganathan , Sanjeev Jahagirdar
Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.
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公开(公告)号：US20190087999A1
公开(公告)日：2019-03-21
申请号：US15710828
申请日：2017-09-20
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Jorge Garcia Pabon , Vasanth Ranganathan , Saikat Mandal , Karol Szerszen , Luis Cruz Camacho , Abhishek R. Appu , Joydeep Ray
CPC classification number: G06T15/005 , G06T1/20 , G06T9/00 , G06T15/40 , G09G5/006 , G09G2360/06 , H04N19/14
Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.
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48.发明申请公开(公告)号：US20180315399A1
公开(公告)日：2018-11-01
申请号：US15819152
申请日：2017-11-21
Applicant: Intel Corporation
Inventor： Himanshu Kaul , Mark A. Anders , Sanu K. Mathew , Anbang Yao , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu , Altug Koker , Kamal Sinha , Balaji Vembu , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Rajkishore Barik , Tsung-Han Lin , Vasanth Ranganathan , Sanjeev Jahagirdar
CPC classification number: G06F9/3001 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/3851 , G06F2207/3824 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/08 , G06N20/00 , G06T15/005 , G09G5/393
Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.
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49.发明申请公开(公告)号：US20180315398A1
公开(公告)日：2018-11-01
申请号：US15787129
申请日：2017-10-18
Applicant: Intel Corporation
Inventor： Himanshu Kaul , Mark A. Anders , Sanu K. Mathew , Anbang Yao , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu , Altug Koker , Kamal Sinha , Balaji Vembu , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Rajkishore Barik , Tsung-Han Lin , Vasanth Ranganathan , Sanjeev Jahagirdar
CPC classification number: G06F9/3001 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/3851 , G06F2207/3824 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/08 , G06N20/00 , G06T15/005 , G09G5/393
Abstract: One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.
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公开(公告)号：US20180308202A1
公开(公告)日：2018-10-25
申请号：US15495054
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Altug Koker , John C. Weast , Mike B. Macpherson , Linda L. Hurd , Sara S. Baghsorkhi , Justin E. Gottschlich , Prasoonkumar Surti , Chandrasekaran Sakthivel , Liwei Ma , Elmoustapha Ould-Ahmed-Vall , Kamal Sinha , Joydeep Ray , Balaji Vembu , Sanjeev Jahagirdar , Vasanth Ranganathan , DUKHWAN Kim
Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.
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