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    MEMORY TIMING CHARACTERIZATION CIRCUITRY
    2.
    发明公开
    MEMORY TIMING CHARACTERIZATION CIRCUITRY 审中-公开

    公开(公告)号：US20240319269A1

    公开(公告)日：2024-09-26

    申请号：US18124338

    申请日：2023-03-21

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Mark A. Anders ,  Ram Kumar Krishnamurthy

    IPC: G01R31/317 ,  G01R31/3185

    CPC classification number: G01R31/31725 ,  G01R31/31713 ,  G01R31/318536

    Abstract: An apparatus includes a plurality of delay generators, a first plurality of flip-flop circuits, a second plurality of flip-flop circuits, and a third plurality of flip-flop circuits. The plurality of delay generators includes a data delay generator, an enable delay generator, and a reference delay generator. The first plurality of flip-flop circuits is coupled to the data delay generator to receive a delayed data input signal, and provide the delayed data input signal to a plurality of data input terminals of a memory circuit. The second plurality of flip-flop circuits is coupled to the enable delay generator to receive a delayed enable signal and provide the delayed enable signal to a plurality of enable terminals of the memory circuit. The third plurality of flip-flop circuits is coupled to an output terminal of the memory circuit. The reference delay generator provides a synchronized clock signal to the flip-flop circuits.

    FLOATING POINT MULTIPLY-ACCUMULATE UNIT FOR DEEP LEARNING
    4.
    发明申请
    FLOATING POINT MULTIPLY-ACCUMULATE UNIT FOR DEEP LEARNING 有权

    公开(公告)号：US20220188075A1

    公开(公告)日：2022-06-16

    申请号：US17688131

    申请日：2022-03-07

    Applicant: Intel Corporation

    Inventor： Arnab Raha ,  Mark A. Anders ,  Raymond Jit-Hung Sung ,  Debabrata Mohapatra ,  Deepak Abraham Mathaikutty ,  Ram K. Krishnamurthy ,  Himanshu Kaul

    IPC: G06F7/544 ,  G06F7/483 ,  G06N3/08

    Abstract: A FPMAC operation has two operands: an input operand and a weight operand. The operands may have a format of FP16, BF16, or INT8. Each operand is split into two portions. The two portions are stored in separate storage units. Then operands are transferred to register files of a PE, with each register file storing bits of an operand sequentially. The PE performs the FPMAC operation based on the operands. The PE may include an FPMAC unit configured to compute an individual partial sum of the PE. The PE may also include an FP adder to accumulate the individual partial sum with other data, such as an output from another PE or an output form another PE array. The FP adder may be fused with the FPMAC unit in a single circuit that can do speculative alignment and has separate critical paths for alignment and normalization.

    Scalable crossbar apparatus and method for arranging crossbar circuits
    8.
    发明授权
    Scalable crossbar apparatus and method for arranging crossbar circuits 有权
    用于布置横梁电路的可伸缩横梁装置和方法

    公开(公告)号：US09577634B2

    公开(公告)日：2017-02-21

    申请号：US14751060

    申请日：2015-06-25

    Applicant: Intel Corporation

    Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

    IPC: H03K19/173 ,  H03K19/00 ,  H03K19/177

    CPC classification number: H03K19/0008 ,  H03K19/17704 ,  H03K19/17744

    Abstract: Described is an apparatus (e.g., a router) which comprises: multiple ports; and a plurality of crossbar circuits arranged such that at least one crossbar circuit receives all interconnects associated with a data bit of the multiple ports and is operable to re-route signals on those interconnects.

    Abstract translation: 描述了一种装置（例如，路由器），其包括：多个端口; 以及布置成使得至少一个交叉电路接收与多个端口的数据位相关联的所有互连并且可操作以在那些互连上重新路由信号的多个交叉电路电路。

    PARALLEL DIRECTION DECODE CIRCUITS FOR NETWORK-ON-CHIP
    9.
    发明申请
    PARALLEL DIRECTION DECODE CIRCUITS FOR NETWORK-ON-CHIP 有权
    并行线路解码电路

    公开(公告)号：US20160182367A1

    公开(公告)日：2016-06-23

    申请号：US14574106

    申请日：2014-12-17

    Applicant: Intel Corporation

    Inventor： Mark A. Anders ,  Gregory K. Chen ,  Himanshu Kaul

    IPC: H04L12/721 ,  H04L12/773 ,  H04L12/801 ,  H04L12/933

    CPC classification number: H04L45/72 ,  H04L45/16 ,  H04L45/60 ,  H04L47/33 ,  H04L49/109 ,  H04L49/25

    Abstract: A first packet and a first direction associated with the first packet are received. The first packet is forwarded to an output port of a plurality of output ports of the first router based on the first direction associated with the first packet. A second direction associated with the first packet is determined. The second direction is based at least on an address of the first packet. The first packet and the second direction are forwarded through the output port of the first router to a second router.

    Abstract translation: 接收与第一分组相关联的第一分组和第一方向。 基于与第一分组相关联的第一方向，第一分组被转发到第一路由器的多个输出端口的输出端口。 确定与第一分组相关联的第二方向。 第二方向至少基于第一分组的地址。 第一分组和第二方向通过第一路由器的输出端口转发到第二路由器。

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