公开(公告)号：US20190026856A1

公开(公告)日：2019-01-24

申请号：US16120591

申请日：2018-09-04

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Prasoonkumar P. Surti ,  Kamal Sinha ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Bhushan M. Borole ,  Wenyin Fu

IPC: G06T1/60 ,  G06T1/20 ,  G06T15/00

Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.

公开(公告)号：US10158346B2

公开(公告)日：2018-12-18

申请号：US15488628

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Anupama A. Thaploo ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: H03K3/012 ,  H03K3/356 ,  H03K19/21

Abstract: A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.

公开(公告)号：US20180300045A1

公开(公告)日：2018-10-18

申请号：US15488998

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole

IPC: G06F3/0484 ,  G06T1/20 ,  G09G5/10

Abstract: Methods and apparatus relating to techniques for provision of active window rendering optimization and display are described. In an embodiment, a processor is caused to render an active portion of a display device prior to an inactive portion of the display device based at least in part on comparison of a determined size of the active portion of the display device with a threshold value. Furthermore, the active portion of the display device may include a portion of the display device that is being viewed by a user or otherwise a portion of the display device with which a user is interacting. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180293695A1

公开(公告)日：2018-10-11

申请号：US15483236

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Abhishek Venkatesh ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  Altug Koker ,  Aravindh V. Anantaraman ,  Pattabhiraman P. K. ,  Abhishek R. Appu ,  Joydeep Ray ,  Kamal Sinha ,  Vasanth Ranganathan ,  Bhushan M. Borole ,  Wenyin Fu ,  Eric J. Hoekstra ,  Linda L. Hurd

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005

Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

公开(公告)号：US09250910B2

公开(公告)日：2016-02-02

申请号：US14040472

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Linda L. Hurd ,  Wenyin Fu ,  Josh B. Mastronarde ,  Pradeep K. Golconda ,  Shalini Sankar ,  Eric C. Samson

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F9/38 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/325 ,  Y02D10/126

Abstract: Methods and apparatus relating to a current change mitigation policy for limiting voltage droop in graphics logic are described. In an embodiment, logic inserts one or more bubbles in one or more Execution Unit (EU) logic pipelines or one or more sampler logic pipelines of a processor. The bubbles at least temporarily reduce execution of operations in one or more subsystems of the processor based at least partially on a comparison of a first value and one or more clamping threshold values. The first value is determined based at least partially on a summation of products of one or more event counts and dynamic capacitance weights for one or more subsystems of the processor. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与用于限制图形逻辑中的电压下降的当前变化缓解策略有关的方法和装置。 在一个实施例中，逻辑在一个或多个执行单元（EU）逻辑管线或处理器的一个或多个采样器逻辑管线中插入一个或多个气泡。 至少部分地基于第一值和一个或多个钳位阈值的比较，气泡至少暂时地减少处理器的一个或多个子系统中的操作的执行。 至少部分地基于处理器的一个或多个子系统的一个或多个事件计数和动态电容权重的乘积的总和确定第一值。 还公开并要求保护其他实施例。

公开(公告)号：US12124310B2

公开(公告)日：2024-10-22

申请号：US18339827

申请日：2023-06-22

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G09G3/06 ,  G06F1/3203 ,  G06F1/3209 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F1/324 ,  G06F3/01 ,  G06F11/07 ,  G06F11/30 ,  H04W52/02 ,  H04M1/72448

CPC classification number: G06F1/3209 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F1/324 ,  G06F3/01 ,  G06F11/0781 ,  G06F11/3062 ,  H04W52/0258 ,  H04M1/72448 ,  Y02D10/00 ,  Y02D30/70

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240257294A1

公开(公告)日：2024-08-01

申请号：US18436494

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F8/41 ,  G06F9/455 ,  G06F9/50 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

CPC classification number: G06T1/20 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06F8/41 ,  G06F2009/45583

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

公开(公告)号：US11922535B2

公开(公告)日：2024-03-05

申请号：US18168207

申请日：2023-02-13

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/50 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06F8/41

CPC classification number: G06T1/20 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06F8/41 ,  G06F2009/45583

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

公开(公告)号：US20240004713A1

公开(公告)日：2024-01-04

申请号：US18363339

申请日：2023-08-01

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Altug KOKER ,  Balaji VEMBU ,  Joydeep RAY ,  Kamal SINHA ,  Prasoonkumar SURTI ,  Kiran C. VEERNAPU ,  Subramaniam MAIYURAN ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06F9/5016 ,  G06F9/5044 ,  G06F1/329 ,  G06F9/4893 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  Y02D10/00 ,  G06T2200/28

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230260072A1

公开(公告)日：2023-08-17

申请号：US18168207

申请日：2023-02-13

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/50 ,  G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06T1/20 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06F8/41

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.