公开(公告)号：US20240004713A1

公开(公告)日：2024-01-04

申请号：US18363339

申请日：2023-08-01

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Altug KOKER ,  Balaji VEMBU ,  Joydeep RAY ,  Kamal SINHA ,  Prasoonkumar SURTI ,  Kiran C. VEERNAPU ,  Subramaniam MAIYURAN ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06F9/5016 ,  G06F9/5044 ,  G06F1/329 ,  G06F9/4893 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  Y02D10/00 ,  G06T2200/28

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230359499A1

公开(公告)日：2023-11-09

申请号：US18195230

申请日：2023-05-09

Applicant: Intel Corporation

Inventor： James VALERIO ,  Vasanth RANGANATHAN ,  Joydeep RAY ,  Rahul A. KULKARNI ,  Abhishek R. APPU ,  Jeffery S. BOLES ,  Hema C. NALLURI

IPC: G06F9/50 ,  G06F9/48 ,  G06T1/20 ,  G06F9/38

CPC classification number: G06F9/5038 ,  G06F9/4881 ,  G06T1/20 ,  G06F9/3822 ,  G06F9/3867 ,  G06F9/5066

Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.

公开(公告)号：US20200278938A1

公开(公告)日：2020-09-03

申请号：US16700853

申请日：2019-12-02

Applicant: INTEL CORPORATION

Inventor： Balaji VEMBU ,  Altug KOKER ,  Joydeep RAY ,  Abhishek R. APPU ,  Pattabhiraman K ,  Niranjan L. COORAY

IPC: G06F13/16 ,  G06F13/40 ,  G06T1/60 ,  G06F9/50

Abstract: An apparatus and method for dynamic provisioning and traffic control on a memory fabric. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated set of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment; and a plurality of queues associated with each VM at different levels of a memory interconnection fabric, the queues for a first VM to store memory traffic for that VM at the different levels of the memory interconnection fabric; arbitration hardware logic coupled to the plurality of queues and distributed across the different levels of the memory interconnection fabric, the arbitration hardware logic to cause memory traffic to be blocked from one or more upstream queues of the first VM upon detecting that a downstream queue associated with the first VM is full or at a specified threshold.

公开(公告)号：US20200005427A1

公开(公告)日：2020-01-02

申请号：US16505555

申请日：2019-07-08

Applicant: INTEL CORPORATION

Inventor： Abhishek R. APPU ,  Joydeep RAY ,  Altug KOKER ,  Balaji VEMBU ,  Pattabhiraman K. ,  Matthew B. CALLAWAY

IPC: G06T1/60 ,  G06F9/455 ,  G06F9/48 ,  G06T15/00 ,  G06F9/50

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

公开(公告)号：US20210287327A1

公开(公告)日：2021-09-16

申请号：US17182256

申请日：2021-02-23

Applicant: INTEL CORPORATION

Inventor： Abhishek R. APPU ,  Joydeep RAY ,  Altug KOKER ,  Balaji VEMBU ,  Pattabhiraman K ,  Matthew B. CALLAWAY

IPC: G06T1/60 ,  G06T15/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/48

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

公开(公告)号：US20200320177A1

公开(公告)日：2020-10-08

申请号：US16792822

申请日：2020-02-17

Applicant: INTEL CORPORATION

Inventor： Joydeep RAY ,  Abhishek R. APPU ,  Pattabhiraman K ,  Balaji VEMBU ,  Altug KOKER

IPC: G06F21/10 ,  G06F12/14 ,  G06F12/0895 ,  G06F9/455 ,  G06F12/0815 ,  G06T15/00 ,  H04N19/00 ,  H04N21/4405

Abstract: An apparatus and method for protecting content in a graphics processor. For example, one embodiment of an apparatus comprises: encode/decode circuitry to decode protected audio and/or video content to generate decoded audio and/or video content; a graphics cache of a graphics processing unit (GPU) to store the decoded audio and/or video content; first protection circuitry to set a protection attribute for each cache line containing the decoded audio and/or video data in the graphics cache; a cache coherency controller to generate a coherent read request to the graphics cache; second protection circuitry to read the protection attribute to determine whether the cache line identified in the read request is protected, wherein if it is protected, the second protection circuitry to refrain from including at least some of the data from the cache line in a response.

公开(公告)号：US20200310883A1

公开(公告)日：2020-10-01

申请号：US16367056

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： James VALERIO ,  Vasanth RANGANATHAN ,  Joydeep RAY ,  Rahul A. KULKARNI ,  Abhishek R. APPU ,  Jeffery S. BOLES ,  Hema C. NALLURI

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/38 ,  G06T1/20

Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.

公开(公告)号：US20240045830A1

公开(公告)日：2024-02-08

申请号：US18450685

申请日：2023-08-16

Applicant: Intel Corporation

Inventor： Joydeep RAY ,  Aravindh ANANTARAMAN ,  Abhishek R. APPU ,  Altug KOKER ,  Elmoustapha OULD-AHMED-VALL ,  Valentin ANDREI ,  Subramaniam MAIYURAN ,  Nicolas GALOPPO VON BORRIES ,  Varghese GEORGE ,  Mike MACPHERSON ,  Ben ASHBAUGH ,  Murali RAMADOSS ,  Vikranth VEMULAPALLI ,  William SADLER ,  Jonathan PEARCE ,  Sungye KIM

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

CPC classification number: G06F15/8069 ,  G06F9/30163 ,  G06F9/3877 ,  G06T15/005 ,  G06F9/3836

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230297419A1

公开(公告)日：2023-09-21

申请号：US17699992

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Joydeep RAY ,  Karthik VAIDYANATHAN ,  Sreedhar CHALASANI ,  Vasanth RANGANATHAN

IPC: G06F9/48 ,  G06F9/50 ,  G06F12/0891

CPC classification number: G06F9/4881 ,  G06F9/505 ,  G06F9/5016 ,  G06F12/0891

Abstract: Bank aware thread scheduling and early dependency clearing techniques are described herein. In one example, bank aware thread scheduling involves arbitrating and scheduling threads based on the cache bank that is to be accessed by the instructions to avoiding bank conflicts. Early dependency clearing involves clearing dependencies for cache loads in a scoreboard before the data is loaded. In early dependency clearing for loads, delays in operation can be reduced by clearing dependencies before data is required from the cache.

公开(公告)号：US20220309731A1

公开(公告)日：2022-09-29

申请号：US17839303

申请日：2022-06-13

Applicant: Intel Corporation

Inventor： Joydeep RAY ,  Abhishek R. APPU ,  Pattabhiraman K ,  Balaji VEMBU ,  Altug KOKER ,  Niranjan L. COORAY ,  Josh B. MASTRONARDE

IPC: G06T15/00 ,  G06F9/455 ,  G06T1/60 ,  G09G5/36 ,  G09G5/00 ,  G09G5/393 ,  G06F9/48 ,  G06F9/50

Abstract: An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.