公开(公告)号：US20220005752A1

公开(公告)日：2022-01-06

申请号：US16919654

申请日：2020-07-02

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A method of frame handling during semiconductor package production includes: providing a lead frame having leads secured to a periphery of the lead frame by first tie bars; providing a multi-gauge spacer frame having spacers secured to a periphery of the spacer frame by second tie bars, the spacers being thicker than the second tie bars; and aligning the multi-gauge spacer frame with the lead frame such that the spacers and the second tie bars of the multi-gauge spacer frame do not contact the leads of the lead frame. A power semiconductor module and a method of assembling a power semiconductor module are also described.

公开(公告)号：US10453771B2

公开(公告)日：2019-10-22

申请号：US15709493

申请日：2017-09-20

Applicant: Infineon Technologies AG ,  HYUNDAI Motor Company ,  Kia Motor Corporation

Inventor： Andreas Grassmann ,  Juergen Hoegerl ,  Kiyoung Jang ,  Ivan Nikitin

IPC: H01L23/495 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00 ,  H01L25/18

Abstract: A package comprising at least one electronic chip, a first heat removal body thermally coupled to a first main surface of the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and part of the first heat removal body, wherein at least part of a surface of the first heat removal body is roughened.

公开(公告)号：US10410949B2

公开(公告)日：2019-09-10

申请号：US15709493

申请日：2017-09-20

Applicant: Infineon Technologies AG ,  HYUNDAI Motor Company ,  Kia Motor Corporation

Inventor： Andreas Grassmann ,  Juergen Hoegerl ,  Kiyoung Jang ,  Ivan Nikitin

IPC: H01L23/495 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00 ,  H01L25/18

Abstract: A package comprising at least one electronic chip, a first heat removal body thermally coupled to a first main surface of the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and part of the first heat removal body, wherein at least part of a surface of the first heat removal body is roughened.

公开(公告)号：US20190157192A1

公开(公告)日：2019-05-23

申请号：US16238973

申请日：2019-01-03

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Juergen Hoegerl ,  Angela Kessler ,  Ivan Nikitin

IPC: H01L23/495 ,  H01L23/373 ,  H01L21/48 ,  H01L23/00

Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.

公开(公告)号：US09847274B2

公开(公告)日：2017-12-19

申请号：US15375855

申请日：2016-12-12

Applicant: Infineon Technologies AG

Inventor： Frank Winter ,  Ottmar Geitner ,  Ivan Nikitin ,  Jürgen Högerl

IPC: H01L23/433 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/4334 ,  H01L21/4871 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/8384 ,  H05K1/185 ,  H05K3/4608 ,  Y10T29/49002

Abstract: According to an exemplary aspect an electronic module is provided, wherein the electronic module comprises an electronic chip comprising at least one electronic component, a spacing element comprising a main surface arranged on the electronic chip and being in thermally conductive connection with the at least one electronic component, and a mold compound at least partially enclosing the electronic chip and the spacing element, wherein the spacing element comprises a lateral surface which is in contact to the mould compound and comprises surface structures.

公开(公告)号：US20160211226A1

公开(公告)日：2016-07-21

申请号：US14987820

申请日：2016-01-05

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Joachim Mahler ,  Ivan Nikitin

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/4832 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments, an integrated circuit is provided. The integrated circuit may include a semiconductor chip and an electrically conductive composite material fixed to the semiconductor chip, wherein the electrically conductive composite material may include a metal, and wherein a coefficient of thermal expansion (CTE) value of the electrically conductive composite material may be lower than the CTE value of the metal.

Abstract translation: 在各种实施例中，提供集成电路。 集成电路可以包括固定到半导体芯片的半导体芯片和导电复合材料，其中导电复合材料可以包括金属，并且其中导电复合材料的热膨胀系数（CTE）值可以是 低于金属的CTE值。

公开(公告)号：US08816500B2

公开(公告)日：2014-08-26

申请号：US13715868

申请日：2012-12-14

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Ivan Nikitin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/562 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face wherein the second main face is the backside of the semiconductor chip. Further, the semiconductor device includes an electrically conductive layer, in particular an electrically conductive layer, arranged on a first region of the second main face of the semiconductor chip. Further, the semiconductor device includes a polymer structure arranged on a second region of the second main face of the semiconductor chip, wherein the second region is a peripheral region of the second main face of the semiconductor chip and the first region is adjacent to the second region.

Abstract translation: 半导体器件包括半导体芯片，其包括第一主面和第二主面，其中第二主面是半导体芯片的背面。 此外，半导体器件包括布置在半导体芯片的第二主面的第一区域上的导电层，特别是导电层。 此外，半导体器件包括布置在半导体芯片的第二主面的第二区域上的聚合物结构，其中第二区域是半导体芯片的第二主面的周边区域，并且第一区域与第二区域的第二区域相邻 地区。

公开(公告)号：US20140167266A1

公开(公告)日：2014-06-19

申请号：US13715868

申请日：2012-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Manfred Schneegans ,  Ivan Nikitin

IPC: H01L21/50 ,  H01L23/29

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/562 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face wherein the second main face is the backside of the semiconductor chip. Further, the semiconductor device includes an electrically conductive layer, in particular an electrically conductive layer, arranged on a first region of the second main face of the semiconductor chip. Further, the semiconductor device includes a polymer structure arranged on a second region of the second main face of the semiconductor chip, wherein the second region is a peripheral region of the second main face of the semiconductor chip and the first region is adjacent to the second region.

Abstract translation: 半导体器件包括半导体芯片，其包括第一主面和第二主面，其中第二主面是半导体芯片的背面。 此外，半导体器件包括布置在半导体芯片的第二主面的第一区域上的导电层，特别是导电层。 此外，半导体器件包括布置在半导体芯片的第二主面的第二区域上的聚合物结构，其中第二区域是半导体芯片的第二主面的周边区域，并且第一区域与第二区域的第二区域相邻 地区。

公开(公告)号：US20140021634A1

公开(公告)日：2014-01-23

申请号：US13944595

申请日：2013-07-17

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Joachim Mahler

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/492 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/80 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/83

Abstract: A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.

Abstract translation: 一种方法包括提供具有第一空腔的载体，提供具有附着到电介质箔的金属层的电介质箔，将第一半导体芯片放置在载体的第一腔中，以及将电介质箔施加到载体上。