公开(公告)号：US11862533B2

公开(公告)日：2024-01-02

申请号：US17557168

申请日：2021-12-21

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Wolfram Hable ,  Juergen Hoegerl ,  Ivan Nikitin ,  Achim Strass

IPC: H01L23/42 ,  H01L23/495 ,  H01L23/552 ,  H01L23/373 ,  H01L23/473 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/42 ,  H01L23/3735 ,  H01L23/473 ,  H01L23/49531 ,  H01L23/552 ,  H01L23/3121 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00

Abstract: A package includes: at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip; a shielding layer on at least part of an external surface of the encapsulant; and a first heat removal body thermally coupled to the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip to a cooling fluid. The encapsulant has a surface portion that extends in a surface region extending laterally directly adjacent to the first heat removal body. The surface portion of the encapsulant delimits part of a cooling cavity configured to guide the cooling fluid. The shielding layer covers the surface portion of the encapsulant. A corresponding electronic device, method of manufacturing the package, method of manufacturing the electronic device, vehicle, and method of using the electronic device are also described.

公开(公告)号：US20230361088A1

公开(公告)日：2023-11-09

申请号：US18130952

申请日：2023-04-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Bäßler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L25/072 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/48

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.

公开(公告)号：US11626351B2

公开(公告)日：2023-04-11

申请号：US17158234

申请日：2021-01-26

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Timo Bohnenberger ,  Andreas Grassmann ,  Martin Mayer ,  Alexander Roth ,  Franz Zollner

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/28 ,  H01L21/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  H01L23/36 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor die, an encapsulant body of electrically insulating material that encapsulates the semiconductor die, a thermal conduction plate comprising an outer surface that is exposed from the encapsulant body, a region of thermal interface material interposed between the thermal conduction plate and the semiconductor die, the region of thermal interface material being a liquid or semi-liquid, and a barrier that is configured to prevent the thermal interface material of the region from flowing laterally across the barrier.

公开(公告)号：US20220262693A1

公开(公告)日：2022-08-18

申请号：US17177703

申请日：2021-02-17

Applicant: Infineon Technologies AG

Inventor： Oliver Markus Kreiter ,  Ludwig Busch ,  Angel Enverga ,  Mei Fen Hiew ,  Tian See Hoe ,  Elvis Keli ,  Kean Ming Koe ,  Sanjay Kumar Murugan ,  Michael Niendorf ,  Ivan Nikitin ,  Bernhard Stiller ,  Thomas Stoek ,  Ke Yan Tean

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.

公开(公告)号：US20220238422A1

公开(公告)日：2022-07-28

申请号：US17158234

申请日：2021-01-26

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Timo Bohnenberger ,  Andreas Grassmann ,  Martin Mayer ,  Alexander Roth ,  Franz Zollner

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor die, an encapsulant body of electrically insulating material that encapsulates the semiconductor die, a thermal conduction plate comprising an outer surface that is exposed from the encapsulant body, a region of thermal interface material interposed between the thermal conduction plate and the semiconductor die, the region of thermal interface material being a liquid or semi-liquid, and a barrier that is configured to prevent the thermal interface material of the region from flowing laterally across the barrier

公开(公告)号：US20210398887A1

公开(公告)日：2021-12-23

申请号：US16907734

申请日：2020-06-22

Applicant: Infineon Technologies AG

Inventor： Michael Niendorf ,  Ludwig Busch ,  Oliver Markus Kreiter ,  Christian Neugirg ,  Ivan Nikitin

IPC: H01L23/495 ,  H01L23/00

Abstract: A power semiconductor module includes a leadframe having a first die pad, a second die pad separated from the first die pad, a first power lead formed as an extension of the first die pad, a second power lead separated from the first and second die pads, and a first connection region formed as an extension of the second power lead alongside the second die pad. A first plurality of power semiconductor dies is attached to the first die pad and electrically coupled in parallel. A second plurality of power semiconductor dies is attached to the second die pad and electrically coupled in parallel. A first electrical connection extends between the first plurality of power semiconductor dies and the second die pad in a first direction. A second electrical connection extends between the second plurality of power semiconductor dies and the first connection region in the first direction.

公开(公告)号：US11075185B2

公开(公告)日：2021-07-27

申请号：US16575006

申请日：2019-09-18

Applicant: Infineon Technologies AG

Inventor： Chii Shang Hong ,  Ivan Nikitin ,  Wei Han Koo ,  Chiew Li Tai

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/367 ,  H01L23/31

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.

公开(公告)号：US09532459B2

公开(公告)日：2016-12-27

申请号：US13964263

申请日：2013-08-12

Applicant: Infineon Technologies AG

Inventor： Frank Winter ,  Ottmar Geitner ,  Ivan Nikitin ,  Juergen Hoegerl

IPC: H05K1/18 ,  H05K3/46

CPC classification number: H01L23/4334 ,  H01L21/4871 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/8384 ,  H05K1/185 ,  H05K3/4608 ,  Y10T29/49002

Abstract: According to an exemplary aspect an electronic module is provided, wherein the electronic module comprises an electronic chip comprising at least one electronic component, a spacing element comprising a main surface arranged on the electronic chip and being in thermally conductive connection with the at least one electronic component, and a mold compound at least partially enclosing the electronic chip and the spacing element, wherein the spacing element comprises a lateral surface which is in contact to the mold compound and comprises surface structures.

Abstract translation: 根据示例性方面，提供一种电子模块，其中所述电子模块包括电子芯片，该电子芯片包括至少一个电子元件，间隔元件，包括布置在所述电子芯片上并与所述至少一个电子元件导热连接的主表面 以及至少部分地包围电子芯片和间隔元件的模具化合物，其中间隔元件包括与模具化合物接触并包括表面结构的侧表面。

公开(公告)号：US11646258B2

公开(公告)日：2023-05-09

申请号：US16944303

申请日：2020-07-31

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Thomas Basler ,  Reinhold Bayerer ,  Ivan Nikitin

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/56 ,  H01L21/48 ,  H01L23/29

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/293 ,  H01L23/66 ,  H01L2223/6605

Abstract: An electronic device and method is disclosed. In one example, the electronic device includes an electrically insulating material, a first load electrode arranged on a first surface of the electrically insulating material, and a second load electrode arranged on a second surface of the electrically insulating material opposite to the first surface, wherein the load electrodes are separated by the electrically insulating material along the entire length on which the load electrodes have opposite sections, wherein surfaces of the load electrodes facing away from the electrically insulating material are uncovered by the electrically insulating material.

公开(公告)号：US20230121335A1

公开(公告)日：2023-04-20

申请号：US18086950

申请日：2022-12-22

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Peter Luniewski

IPC: H01L23/498 ,  H01R12/58 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A method of forming a semiconductor device includes providing a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, mounting one or more semiconductor dies on a portion of the structured metallization layer, forming an encapsulant body of electrically insulating material that covers the power electronics carrier and encapsulates the one or more semiconductor dies, securing a press-fit connector to the power electronics carrier with a base portion of the press-fit connector being disposed within an opening in the encapsulant body and with an interfacing end of the press-fit connector being electrically accessible from outside the encapsulant body.