-
公开(公告)号：US09183144B2
公开(公告)日：2015-11-10
申请号：US13715613
申请日：2012-12-14
Applicant: Intel Corporation
Inventor： Ren Wang , Ahmad Samih , Eric Delano , Pinkesh J. Shah , Zeshan A. Chishti , Christian Maciocco , Tsung-Yuan Charlie Tai
CPC classification number: G06F12/0802 , G06F1/32 , G06F1/3215 , G06F1/3225 , G06F1/3243 , G06F1/3287 , G06F12/0811 , G06F2212/1028 , Y02D10/13
Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.
-
公开(公告)号：US09176875B2
公开(公告)日：2015-11-03
申请号：US13785228
申请日：2013-03-05
Applicant: Intel Corporation
Inventor： Ren Wang , Ahmad Samih , Eric Delano , Pinkesh J. Shah , Zeshan A. Chishti , Christian Maciocco , Tsung-Yuan Charlie Tai
CPC classification number: G06F12/0802 , G06F1/32 , G06F1/3215 , G06F1/3225 , G06F1/3243 , G06F1/3287 , G06F12/0811 , G06F2212/1028 , Y02D10/13
Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括多个瓦片，每个瓦片包括核心和瓦片高速缓存层级。 该瓦片高速缓存层级包括第一级高速缓存，中级缓存（MLC）和最后级高速缓存（LLC），并且这些高速缓存中的每一个对于该瓦片是私有的。 耦合到瓦片的控制器包括高速缓存功率控制逻辑，用于至少部分地基于该信息来接收关于瓦片的核心和瓦片高速缓存层级的利用信息，并且使瓦片的LLC独立地进行电源门控。 描述和要求保护其他实施例。
-
公开(公告)号：US20230095715A1
公开(公告)日：2023-03-30
申请号：US17484811
申请日：2021-09-24
Applicant: Intel Corporation
Inventor： Amar Srivastava , Christian Maciocco , Kshitij Arun Doshi
IPC: H04W12/121 , H04W72/04 , H04W12/48
Abstract: An apparatus and system to provide separate network slices for security events are described. A dedicated secure network slice is provided for PDP data from a UE. The network slice is used for detecting security issues and sending security-related information to clients. The communications in the dedicated network slice are associated with a special PDP context used by the UE to interface with the network slice. Once the UE has detected a security issue or has been notified of the security issue on the network or remote servers, the UE uses a special PDP service, and is able to stop uplink/downlink channels, close running applications and enter into a sate mode, cut off connections to the networks, and try to determine alternate available connectivity.
-
公开(公告)号：US11507643B2
公开(公告)日：2022-11-22
申请号：US16373300
申请日：2019-04-02
Applicant: Intel Corporation
Inventor： Malini K. Bhandaru , Kapil Sood , Christian Maciocco , Isaku Yamahata , Yunhong Jiang
Abstract: At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system cause the system to send a unique identifier to a license server, establish a secure channel based on the unique identifier, request a license for activating an appliance from a license server over the secure channel, receive license data from the license server over the secure channel; determine whether the license is valid, and activate the appliance in response to a determination that the license data is valid.
-
公开(公告)号：US11005884B2
公开(公告)日：2021-05-11
申请号：US15720821
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Sameh Gobriel , Christian Maciocco , Byron Marohn , Ren Wang , Tsung-Yuan C. Tai
Abstract: A computing apparatus for providing a node within a distributed network function, including: a hardware platform; a network interface to communicatively couple to at least one other peer node of the distributed network function; a distributor function including logic to operate on the hardware platform, including a hashing module configured to receive an incoming network packet via the network interface and perform on the incoming network packet a first-level hash of a two-level hash, the first level hash being a lightweight hash with respect to a second-level hash, the first level hash to deterministically direct a packet to one of the nodes of the distributed network function as a directed packet; and a denial of service (DoS) mitigation engine to receive notification of a DoS attack, identify a DoS packet via the first-level hash, and prevent the DoS packet from reaching the second-level hash.
-
Patent Agency Ranking
公开(公告)号：US20210105335A1
公开(公告)日：2021-04-08
申请号：US16997278
申请日：2020-08-19
Applicant: Intel Corporation
Inventor： Sebastian Schoenberg , Andrew Stephen Brown , Srikathyayani Srikanteswara , Jessica C. McCarthy , Eve M. Schooler , Christian Maciocco , Hassnaa Moustafa , Nageen Himayat , Rath Vannithamby , David John Zage
IPC: H04L29/08 , G06F16/23 , H04L12/24 , G06F16/957 , H04L12/26 , H04L29/06 , H04L12/841 , H04L12/773 , H04L12/741 , H04L12/813 , H04L29/12 , H04L12/721 , H04L12/911 , H04L12/715
Abstract: Generally discussed herein are systems, devices, and methods for populating a cache in an information-centric network. A device of an ICN can include a content store including published content and attributes of the published content stored thereon, the attributes including at least two of a device from which the content originated attribute, a lineage attribute, and a service level agreement attribute, and content processing circuitry coupled to the content store, the content processing circuitry configured to manage the published content based on the attributes.
-
公开(公告)号：US10805418B2
公开(公告)日：2020-10-13
申请号：US16511855
申请日：2019-07-15
Applicant: Intel Corporation
Inventor： Vallabhajosyula S. Somayazulu , Eve M. Schooler , Hassnaa Moustafa , Andrew Stephen Brown , Rath Vannithamby , Srikathyayani Srikanteswara , David John Zage , Ren Wang , Christian Maciocco , David E. Ott , Jeffrey Christopher Sedayao , David E. Cohen , Sung Lee
IPC: H04L29/08 , H04L12/26 , G06F16/23 , H04L12/24 , G06F16/957 , H04L29/06 , H04L12/841 , H04L12/773 , H04L12/741 , H04L12/813 , H04L29/12 , H04L12/721 , H04L12/911 , H04L12/715
Abstract: Generally discussed herein are systems, devices, and methods for managing content of an information centric network (ICN). A component of an ICN can include a memory including an extended content store that includes content from at least one other component of the ICN, and first attributes of the content, the first attributes including a content popularity value that indicates a number of requests for the content, and processing circuitry to increment the content popularity value in response to a transmission of a first content packet that includes the content, the first content packet transmitted in response to receiving an interest packet.
-
公开(公告)号：US20200174811A1
公开(公告)日：2020-06-04
申请号：US16786915
申请日：2020-02-10
Applicant: Intel Corporation
Inventor： Ashok Sunder Rajan , Richard A. Uhlig , Rajendra S. Yavatkar , Tsung-Yuan C. Tai , Christian Maciocco , Jeffrey R. Jackson , Daniel J. Dahle
Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
-
公开(公告)号：US10558481B2
公开(公告)日：2020-02-11
申请号：US15812888
申请日：2017-11-14
Applicant: INTEL CORPORATION
Inventor： Ashok Sunder Rajan , Richard A. Uhlig , Rajendra S. Yavatkar , Tsung-Yuan C. Tai , Christian Maciocco , Jeffrey R. Jackson , Daniel J. Dahle
Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
-
公开(公告)号：US10394784B2
公开(公告)日：2019-08-27
申请号：US15389218
申请日：2016-12-22
Applicant: INTEL CORPORATION
Inventor： Byron Marohn , Christian Maciocco , Sameh Gobriel , Ren Wang , Wei Shen , Tsung-Yuan Charlie Tai , Saikrishna Edupuganti
IPC: G06F16/22 , G06F3/06 , G06F16/00 , H04L12/701
Abstract: Technologies for managing lookup tables are described. The lookup tables may be used for a two-level lookup scheme for packet processing. When the tables need to be updated with a new key for packet processing, information about the new key may be added to a first-level lookup table and a second-level lookup table. The first-level lookup table may be used to identify a handling node for an obtained packet, and the handling node may perform a second-level table lookup to obtain information for further packet processing. The first lookup table may be replicated on all the nodes in a cluster, and the second-level lookup table may be unique to each node in the cluster. Other embodiments are described herein and claimed.
-
-
-
-
-
-
-
-
-
Search Results
71
records
(took 0.036 seconds)
