公开(公告)号：US11593154B2

公开(公告)日：2023-02-28

申请号：US16228136

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Ahmad Samih ,  Rajshree Chabukswar ,  Russell Fenger ,  Shadi Khasawneh ,  Vijay Dhanraj ,  Muhammad Abozaed ,  Mukund Ramakrishna ,  Atsuo Kuwahara ,  Guruprasad Settuvalli ,  Eugene Gorbatov ,  Monica Gupta ,  Christine M. Lin

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F9/30

Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

公开(公告)号：US09390010B2

公开(公告)日：2016-07-12

申请号：US13715526

申请日：2012-12-14

Applicant: Intel Corporation

Inventor： Ahmad Samih ,  Ren Wang ,  Christian Maciocco ,  Sameh Gobriel ,  Tsung-Yuan Tai

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/0888 ,  Y02D10/13

Abstract: The present disclosure provides techniques for cache management. A data block may be received from an IO interface. After receiving the data block, the occupancy level of a cache memory may be determined. The data block may be directed to a main memory if the occupancy level exceeds a threshold. The data block may be directed to a cache memory if the occupancy level is below a threshold.

Abstract translation: 本公开提供了用于高速缓存管理的技术。 可以从IO接口接收数据块。 在接收到数据块之后，可以确定高速缓冲存储器的占用水平。 如果占用率超过阈值，则数据块可以被引导到主存储器。 如果占用水平低于阈值，则数据块可以被引导到高速缓冲存储器。

公开(公告)号：US09183144B2

公开(公告)日：2015-11-10

申请号：US13715613

申请日：2012-12-14

Applicant: Intel Corporation

Inventor： Ren Wang ,  Ahmad Samih ,  Eric Delano ,  Pinkesh J. Shah ,  Zeshan A. Chishti ,  Christian Maciocco ,  Tsung-Yuan Charlie Tai

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F1/32 ,  G06F1/3215 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0811 ,  G06F2212/1028 ,  Y02D10/13

Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

公开(公告)号：US09176875B2

公开(公告)日：2015-11-03

申请号：US13785228

申请日：2013-03-05

Applicant: Intel Corporation

Inventor： Ren Wang ,  Ahmad Samih ,  Eric Delano ,  Pinkesh J. Shah ,  Zeshan A. Chishti ,  Christian Maciocco ,  Tsung-Yuan Charlie Tai

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F1/32 ,  G06F1/3215 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0811 ,  G06F2212/1028 ,  Y02D10/13

Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个瓦片，每个瓦片包括核心和瓦片高速缓存层级。 该瓦片高速缓存层级包括第一级高速缓存，中级缓存（MLC）和最后级高速缓存（LLC），并且这些高速缓存中的每一个对于该瓦片是私有的。 耦合到瓦片的控制器包括高速缓存功率控制逻辑，用于至少部分地基于该信息来接收关于瓦片的核心和瓦片高速缓存层级的利用信息，并且使瓦片的LLC独立地进行电源门控。 描述和要求保护其他实施例。