公开(公告)号：US10598696B2

公开(公告)日：2020-03-24

申请号：US15083082

申请日：2016-03-28

Applicant: INTEL CORPORATION

Inventor： Joseph D. Stanford ,  David Craig ,  Todd P. Albertson ,  Mohit Mamodia ,  Dingying Xu

IPC: G01R1/067 ,  G01R1/073 ,  G01R3/00

Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.

公开(公告)号：US20160172229A1

公开(公告)日：2016-06-16

申请号：US14568552

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Xavier Brun ,  Arjun Krishnan ,  Mohit Mamodia ,  Dingying Xu

IPC: H01L21/683 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L21/6836 ,  H01L21/304 ,  H01L21/78 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape. The stiffener tape further includes a die attach film attached to the stiffener. Other example forms relate to an electronic assembly that includes a wafer and a stiffener tape attached to the wafer. The stiffener tape includes a die attach film mounted to the wafer. A stiffener is attached to the die attach film and a mounting tape is removably attached to the stiffener. Still other example forms relate to a method that includes forming a stiffener tape which includes a mounting tape, a stiffener removably attached to the mounting tape and a die attach film attached to the stiffener.

Abstract translation: 一些示例性形式涉及用于晶片的加强带。 加强筋包括可拆卸地附接到安装带的安装带和加强件。 加强筋还包括附着在加强件上的管芯附着膜。 其他示例性形式涉及包括晶片和附接到晶片的加强筋的电子组件。 加强筋包括安装在晶片上的管芯附着膜。 加强件附接到管芯附着膜，并且安装带可拆卸地附接到加强件。 另一个示例形式涉及一种方法，其包括形成加强带，该加强带包括安装带，可移除地附接到安装带的加强件和附接到加强件的管芯附着膜。

公开(公告)号：US20250110295A1

公开(公告)日：2025-04-03

申请号：US18478077

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Saikumar Jayaraman ,  Yiqun Bai ,  Fan Fan ,  Dingying Xu

IPC: G02B6/42 ,  C09J171/02

Abstract: A set of optical fibers are set within grooves a substrate to align the optical fibers with a waveguide associated with photonic processing circuitry. The set of optical fibers are adhered within the grooves using a polyethylene oxide (PEO)-based adhesive. The PEO-based adhesive may have a refractive index matched to the refractive index of one or both of the optical fibers or the waveguide.

公开(公告)号：US12230564B2

公开(公告)日：2025-02-18

申请号：US17345912

申请日：2021-06-11

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Tarek A. Ibrahim ,  Karumbu Nathan Meyyappan ,  Valery Ouvarov-Bancalero ,  Dingying Xu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing. The substrate assembly can reduce cost and provide improved overall yield and electrical performance relative to monolithic substrates.

公开(公告)号：US20240264530A1

公开(公告)日：2024-08-08

申请号：US18147472

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ryan Carrazzone ,  Kyle Arrington ,  Brandon Rawlings ,  Bohan Shan ,  Dingying Xu

IPC: G03F7/16 ,  C08G75/20 ,  G03F7/038 ,  G03F7/039

CPC classification number: G03F7/168 ,  C08G75/20 ,  G03F7/038 ,  G03F7/039

Abstract: Light responsive photoresists, and methods of using light responsive photoresists in processes, such as lithography processes. The light responsive photoresists may include a polymer featuring a photocleavable group. Due to the photocleavable group, the polymer may depolymerize when irradiated with one or more wavelengths of light. The depolymerized products may be in the gas phase.

公开(公告)号：US20240222243A1

公开(公告)日：2024-07-04

申请号：US18091555

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Kristof Darmawikarta

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16227

Abstract: An integrated circuit device substrate includes a first glass layer with a redistribution layer mounting region and an integrated circuit device mounting region, wherein a first major surface of the first glass layer is overlain by a first dielectric layer, and wherein the first glass layer includes a first plurality of conductive pillars. A second glass layer is on the redistribution layer mounting region on the first glass layer, wherein the second glass layer includes a second dielectric layer on a second major surface thereof, and wherein the second dielectric layer is bonded to the first dielectric layer on the first major surface of the first glass layer, the second glass layer including a second plurality of conductive pillars electrically interconnected with the first plurality of conductive pillars in the first glass layer.

公开(公告)号：US20240219656A1

公开(公告)日：2024-07-04

申请号：US18089963

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Yiqun Bai ,  Bohan Shan ,  Kyle Jordan Arrington ,  Haobo Chen ,  Dingying Xu ,  Robert Alan May ,  Gang Duan ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram

IPC: G02B6/42 ,  H01L23/15 ,  H01L25/16

CPC classification number: G02B6/4214 ,  H01L23/15 ,  H01L25/167 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240219654A1

公开(公告)日：2024-07-04

申请号：US18089892

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Yiqun Bai ,  Bohan Shan ,  Kyle Jordan Arrington ,  Haobo Chen ,  Dingying Xu ,  Robert Alan May ,  Gang Duan ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram

IPC: G02B6/42 ,  H01L25/16

CPC classification number: G02B6/4214 ,  H01L25/167

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240213169A1

公开(公告)日：2024-06-27

申请号：US18086265

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Jeremy D. Ecton ,  Brandon C. Marin

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L23/64 ,  H10B80/00

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5382 ,  H01L23/5386 ,  H01L23/645 ,  H10B80/00 ,  H01L24/32

Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer including a cavity formed through the glass core layer; a glass core layer active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer; a second buildup layer contacting a second surface of the glass core layer; and a mold layer contacting a surface of the first buildup layer. The mold layer includes a mold layer active component die disposed in the mold layer, and the first buildup layer includes electrically conductive interconnect providing electrical continuity between the glass core layer active component die and the mold layer active component die. The top surface active component die is attached to the top surface of the substrate and electrically connected to the mold layer active component die.

公开(公告)号：US20240112971A1

公开(公告)日：2024-04-04

申请号：US17957359

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Dingying Xu ,  Srinivas Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Haobo Chen ,  Kyle Arrington ,  Bohan Shan

IPC: H01L23/15 ,  H01L21/02 ,  H01L23/495

CPC classification number: H01L23/15 ,  H01L21/02354 ,  H01L23/49506

Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.