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    Technologies for providing inter-kernel flow control for accelerator device kernels
    41.
    发明授权
    Technologies for providing inter-kernel flow control for accelerator device kernels 有权

    公开(公告)号：US10789189B1

    公开(公告)日：2020-09-29

    申请号：US16395777

    申请日：2019-04-26

    Applicant: Intel Corporation

    Inventor： Susanne M. Balle ,  Evan Custodio

    IPC: G06F13/20 ,  G06F13/40

    Abstract: Technologies for providing inter-kernel flow control for accelerator device kernels includes an accelerator device. The accelerator device includes circuitry to determine availability data indicative of an availability of one or more accelerator device kernels in a system. The availability data includes credit data indicative of a number of data packets permitted to be sent from an output port associated with a kernel of the present accelerator device to an input port associated with another accelerator device kernel. The circuitry is also to obtain a data packet to be processed by a target accelerator device kernel in the system. Additionally, the circuitry is to determine, as a function of the credit data, an output port to send the data packet through to provide the data packet to the target accelerator device kernel. Additionally, the circuitry is to send the data packet through the determined output port.

    TECHNOLOGIES FOR PROVIDING FUNCTION AS SERVICE TIERED SCHEDULING AND MAPPING FOR MULTI-OPERATOR ARCHITECTURES
    42.
    发明申请
    TECHNOLOGIES FOR PROVIDING FUNCTION AS SERVICE TIERED SCHEDULING AND MAPPING FOR MULTI-OPERATOR ARCHITECTURES 审中-公开

    公开(公告)号：US20190141121A1

    公开(公告)日：2019-05-09

    申请号：US16234865

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Ned Smith ,  Evan Custodio ,  Suraj Prabhkaran ,  Ignacio Astilleros Diez

    IPC: H04L29/08 ,  H04L12/24 ,  H04L12/14 ,  H04L12/927

    Abstract: Technologies for determining a set of edge resources to offload a workload from a client compute device based on a brokering logic provided by a service provider include a device that includes circuitry that is in communication with edge resources. The circuitry is to receive a brokering logic from a service provider receive a request from a client compute device, wherein the request includes a function to be used to execute the request and one or more parameters associated with the client compute device, determine the one or more parameters, select, as a function of the one or more parameters and the brokering logic, a physical implementation to perform the function, wherein the physical implementation indicates a set of edge resources and a performance level for each edge resource of the set of edge resources, and perform, in response to a selection of the physical implementation, the request using the set of edge resources associated with the physical implementation.

    TECHNOLOGIES FOR PROVIDING EFFICIENT ACCESS TO POOLED ACCELERATOR DEVICES
    43.
    发明申请
    TECHNOLOGIES FOR PROVIDING EFFICIENT ACCESS TO POOLED ACCELERATOR DEVICES 审中-公开

    公开(公告)号：US20190065083A1

    公开(公告)日：2019-02-28

    申请号：US15858557

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： Sujoy Sen ,  Susanne M. Balle ,  Narayan Ranganathan ,  Evan Custodio ,  Paul H. Dormitzer ,  Francesc Guim Bernat

    IPC: G06F3/06 ,  G06F21/62

    Abstract: Technologies for providing efficient access to pooled accelerator devices include an accelerator sled. The accelerator sled includes an accelerator device and a controller connected to the accelerator device. The controller is to provide, to a compute sled, accelerator abstraction data. The accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and defines an access mode usable to access each corresponding memory region. The controller is further to receive, from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode. Additionally, the controller is to convert the request from a first format to a second format that is different from the second format and is usable by the accelerator device to perform the operation. Additionally, the controller is to perform, in response to the request, the operation on the identified memory region of the accelerator device with the corresponding access mode. Other embodiments are also described and claimed.

    INTERFACE DISCOVERY BETWEEN PARTITIONS OF A PROGRAMMABLE LOGIC DEVICE
    44.
    发明申请
    INTERFACE DISCOVERY BETWEEN PARTITIONS OF A PROGRAMMABLE LOGIC DEVICE 审中-公开

    公开(公告)号：US20190042533A1

    公开(公告)日：2019-02-07

    申请号：US15862249

    申请日：2018-01-04

    Applicant: Intel Corporation

    Inventor： Evan Custodio

    IPC: G06F15/78 ,  H03K19/177

    Abstract: Systems, methods, and devices for enhancing the flexibility of an integrated circuit device with partially reconfigurable regions are provided. For example, a discovery interface may determine and/or communicate a suitable logical protocol interface to control data transfer between regions on the integrated circuit device. The techniques provided herein result in more flexible partial reconfiguration options to enable greater compatibility between accelerator hosts and accelerator function units.

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