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公开(公告)号:US20170185561A1
公开(公告)日:2017-06-29
申请号:US14757892
申请日:2015-12-24
Applicant: Intel Corporation
Inventor: James Dinan , Mario Flajslik , Keith Underwood , David Keppel , Ulf Rainer Hanebutte
IPC: G06F15/167 , H04L12/931
CPC classification number: H04L49/35 , G06F15/17331
Abstract: In an example, there is disclosed a compute node, comprising: first one or more logic elements comprising a data producer engine to produce a datum; and a host fabric interface to communicatively couple the compute node to a fabric, the host fabric interface comprising second one or more logic elements comprising a data pulling engine, the data pulling engine to: publish the datum as available; receive a pull request for the datum, the pull request comprising a node identifier for a data consumer; and send the datum to the data consumer via the fabric. There is also disclosed a method of providing a data pulling engine.
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公开(公告)号:US20170093670A1
公开(公告)日:2017-03-30
申请号:US14866536
申请日:2015-09-25
Applicant: Intel Corporation
Inventor: James Dinan , David Keppel
CPC classification number: H04L43/0876 , H04L43/0864 , H04L43/10 , H04L43/106 , H04L43/12 , H04L67/10 , H04L67/1004 , H04L67/22 , H04L69/40
Abstract: Technologies for monitoring communication performance of a high performance computing (HPC) network include a performance probing engine of a source endpoint node of the HPC network. The performance probing engine is configured to generate a probe request that includes a timestamp of the probe request and transmit the probe request to a destination endpoint node of the HPC network communicatively coupled to the source endpoint node via the HPC network. The performance probing engine is additionally configured to receive a probe response from the destination endpoint node via the HPC network and to generate another timestamp that corresponds to the probe request having been received. Further, the performance probing engine is configured to determine a round-trip latency as a function of the probe request and probe response timestamps. Other embodiments are described and claimed.
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公开(公告)号:US20170090979A1
公开(公告)日:2017-03-30
申请号:US14866572
申请日:2015-09-25
Applicant: Intel Corporation
Inventor: James Dinan , Mario Flajslik , Tom St. John
IPC: G06F9/48
CPC classification number: G06F9/46 , G06F9/4881 , G06F9/5027 , G06F9/5038 , G06F2209/484 , G06F2209/485
Abstract: Technologies for integrated thread scheduling include a computing device having a network interface controller (NIC). The NIC is configured to detect and suspend a thread that is being blocked by one or more communication operations. A thread scheduling engine of the NIC is configured to move the suspended thread from a running queue of the system thread scheduler to a pending queue of the thread scheduling engine. The thread scheduling engine is further configured to move the suspended thread from the pending queue to a ready queue of the thread scheduling engine upon determining any dependencies and/or blocking communications operations have completed. Other embodiments are described and claimed.
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