公开(公告)号：US20190385959A1

公开(公告)日：2019-12-19

申请号：US16012371

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01L21/822 ,  H01L27/04 ,  H01F27/28 ,  H01F27/24

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US12087746B2

公开(公告)日：2024-09-10

申请号：US18128952

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Cheng Xu ,  Junnan Zhao ,  Ying Wang ,  Meizi Jiao

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538 ,  H01L25/16 ,  H01L49/02

CPC classification number: H01L25/16 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/528 ,  H01L23/5386 ,  H01L28/40 ,  H01L2224/1623 ,  H01L2224/16265

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US11735537B2

公开(公告)日：2023-08-22

申请号：US17852003

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/645 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US11521914B2

公开(公告)日：2022-12-06

申请号：US16233808

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Cheng Xu ,  Yikang Deng ,  Junnan Zhao ,  Ying Wang ,  Chong Zhang ,  Kyu Oh Lee ,  Chandra Mohan Jha ,  Chia-Pin Chiu

IPC: H01L23/473 ,  H01L21/48

Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.

公开(公告)号：US20220230951A1

公开(公告)日：2022-07-21

申请号：US17715380

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Prithwish Chatterjee ,  Junnan Zhao ,  Sai Vadlamani ,  Ying Wang ,  Rahul Jain ,  Andrew J. Brown ,  Lauren A. Link ,  Cheng Xu ,  Sheng C. Li

IPC: H01L23/498 ,  H01L21/48 ,  H01F27/28 ,  H01F41/04 ,  H01L25/16

Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

公开(公告)号：US11246218B2

公开(公告)日：2022-02-08

申请号：US15910288

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Ying Wang ,  Junnan Zhao ,  Cheng Xu ,  Yikang Deng

IPC: H01L23/495 ,  H05K1/16 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01F41/04 ,  H01F27/28 ,  H01F17/00 ,  H05K3/06 ,  H01L23/00

Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

公开(公告)号：US20200373257A1

公开(公告)日：2020-11-26

申请号：US16990782

申请日：2020-08-11

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Venkata Ramanuja Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01F27/24 ,  H01L27/04 ,  H01F27/28 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US10804188B2

公开(公告)日：2020-10-13

申请号：US16124838

申请日：2018-09-07

Applicant: Intel Corporation

Inventor： Yikang Deng ,  Ying Wang ,  Cheng Xu ,  Chong Zhang ,  Junnan Zhao

IPC: H01L23/498 ,  H01L23/538

Abstract: An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.

公开(公告)号：US20200312738A1

公开(公告)日：2020-10-01

申请号：US16364540

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Junnan Zhao ,  Cheng Xu ,  Zhimin Wan ,  Yikang Deng ,  Chong Zhang ,  Ying Wang

IPC: H01L23/373 ,  H01L21/768 ,  H01L23/367

Abstract: An integrated circuit assembly may be formed having at least one integrated circuit device electrically attached to an electronic substrate. The integrated circuit assembly may further include at least one heat dissipation device attached to the electronic substrate, wherein the at least one heat dissipation device comprises a phase change material within a containment chamber. The at least one integrated circuit device may be thermally connected to the at least one heat dissipation device with at least one heat transfer structure formed in or on the electronic substrate.

公开(公告)号：US10777514B2

公开(公告)日：2020-09-15

申请号：US16012371

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01F27/24 ,  H01L27/04 ,  H01F27/28 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.