公开(公告)号：US20230087810A1

公开(公告)日：2023-03-23

申请号：US17482852

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD ,  Oscar OJEDA ,  Bai NIE ,  Brandon C. MARIN ,  Gang DUAN ,  Jacob VEHONSKY ,  Onur OZKAN ,  Nicholas S. HAEHN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

公开(公告)号：US20210090946A1

公开(公告)日：2021-03-25

申请号：US16578698

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Matthew ANDERSON ,  Adrian BAYRAKTAROGLU ,  Roy DITTLER ,  Benjamin DUONG ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Suddhasattwa NAD ,  Rengarajan SHANMUGAM ,  Marcel WALL

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments herein relate to systems, apparatuses, and/or processes directed to a package or a manufacturing process flow for creating a package that uses multiple seeding techniques to fill vias in the package. Embodiments include a first layer of copper seeding coupled with a portion of the boundary surface and a second layer of copper seeding coupled with the boundary surface or the first layer of copper seeding, where the first layer of copper seeding and the second layer of copper seeding have a combined thickness along the boundary surface that is greater than a threshold value.

公开(公告)号：US20200315023A1

公开(公告)日：2020-10-01

申请号：US16363925

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Kassandra NIKKHAH ,  Joshua MICHALAK ,  Marcel WALL ,  Rahul MANEPALLI ,  Cemil GEYIK ,  Benjamin DUONG ,  Darko GRUJICIC

IPC: H05K3/10 ,  H01L23/538 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first layer of a package substrate and a conductive trace over the first layer of the package substrate. In an embodiment, the conductive trace comprises a conductive body with a first surface over the first layer of the package substrate, a second surface opposite the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, the second surface has a first roughness and the sidewall surfaces have a second roughness that is less than the first roughness.

公开(公告)号：US20200312665A1

公开(公告)日：2020-10-01

申请号：US16363688

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Jeremy ECTON ,  Bai NIE ,  Rahul MANEPALLI ,  Marcel WALL

IPC: H01L21/28 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.

公开(公告)号：US20200251332A1

公开(公告)日：2020-08-06

申请号：US16269357

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Roy DITTLER ,  Darko GRUJICIC ,  Marcel WALL ,  Rahul MANEPALLI

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/285

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.

公开(公告)号：US20180331003A1

公开(公告)日：2018-11-15

申请号：US15776755

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Krishna BHARATH ,  Mathew J. MANUSHAROW ,  Adel A. ELSHERBINI ,  Mihir K. ROY ,  Aleksandar ALEKSOV ,  Yidnekachew S. MEKONNEN ,  Javier SOTO GONZALEZ ,  Feras EID ,  Suddhasattwa NAD ,  Meizi JIAO

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/12 ,  H01L21/486 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.