公开(公告)号：US20220302007A1

公开(公告)日：2022-09-22

申请号：US17204592

申请日：2021-03-17

Applicant: Intel Corporation

Inventor： Santosh Gangal ,  Tin Poay Chuah

IPC: H01L23/498 ,  H01L49/02 ,  H01L21/48 ,  H01L23/00 ,  H05K1/11 ,  H05K1/16

Abstract: Disclosed herein are via plug capacitors for incorporation into electronic substrates, and related methods and devices. Exemplary via plug capacitor structures include a capacitive element within a via extending at least partially through an electronic substrate and first and second electrodes coupled to the capacitive element.

公开(公告)号：US20220015272A1

公开(公告)日：2022-01-13

申请号：US17482244

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Yew San Lim ,  Jeff Ku ,  Boon Ping Koh ,  Min Suet Lim ,  Tin Poay Chuah

IPC: H05K9/00 ,  H05K1/02 ,  H05K7/20

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a radiation shield that includes a zipper. The radiation shield can include a wall that extends from a support structure of the electronic device, a first portion that is coupled to a cold plate over a radiation source, a second portion that is coupled to the wall, and a zipper that can zip the first portion to the second portion together and can unzip to separate the first portion from the second portion

公开(公告)号：US20210385942A1

公开(公告)日：2021-12-09

申请号：US16988759

申请日：2020-08-10

Applicant: Intel Corporation

Inventor： Tai Loong Wong ,  Fern Nee Tan ,  Tin Poay Chuah ,  Min Suet Lim ,  Siang Yeong Tan

IPC: H05K1/02 ,  H05K1/14

Abstract: The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.

公开(公告)号：US11031359B2

公开(公告)日：2021-06-08

申请号：US16462197

申请日：2017-11-20

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Tin Poay Chuah ,  Chin Lee Kuan

IPC: H01R9/00 ,  H01L23/64 ,  H01L23/498 ,  H05K1/18 ,  H05K1/02 ,  H01L23/50 ,  H01L23/13

Abstract: A capacitor loop substrate assembly may include a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects may be formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.

公开(公告)号：US20210144844A1

公开(公告)日：2021-05-13

申请号：US17154551

申请日：2021-01-21

Applicant: Intel Corporation

Inventor： Jaejin Lee ,  Min Suet Lim ,  Luis Paniagua Acuna ,  Tin Poay Chuah

IPC: H05K1/02 ,  H05K1/11

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a shielding layer to be inserted under an inductor footprint to mitigate the impact of electromagnetic interference (EMI) onto electrical traces beneath the shielding layer and under the inductor footprint. In embodiments, the electrical traces may be high-speed input/output (HSIO) traces that may be particularly susceptible to data corruption given the level of EMI. In embodiments, the shielding layer may be a high density metallization shield within dielectric stack-up layers. In embodiments, these layers may use unique via patterns or shaped metal preform shields to enable routing under an inductor at a higher layer of the PCB. Other embodiments may be described and/or claimed.

公开(公告)号：US20210051801A1

公开(公告)日：2021-02-18

申请号：US16887902

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H05K1/14 ,  H01R12/77 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30 ,  H05K3/36

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first rigid substrate, a second rigid substrate, a flexible substrate comprising a first portion attached to the first rigid substrate, a second portion attached to the second rigid substrate, a middle portion connecting the first portion to the second portion, wherein the middle portion is bent, and metallic traces therethrough, and a component forming a direct interface with the middle portion of the flexible substrate, the component electrically coupled to the metallic traces. In selected examples, the device further includes a casing.

公开(公告)号：US10772206B2

公开(公告)日：2020-09-08

申请号：US16513004

申请日：2019-07-16

Applicant: Intel Corporation

Inventor： Chee Ling Wong ,  Wil Choon Song ,  Khang Choong Yong ,  Eng Huat Goh ,  Mohd Muhaiyiddin Bin Abdullah ,  Tin Poay Chuah

IPC: H05K1/11 ,  H05K1/14 ,  H05K1/02

Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

公开(公告)号：US20190006356A1

公开(公告)日：2019-01-03

申请号：US15988958

申请日：2018-05-24

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Jenny Shio Yin Ong ,  Tin Poay Chuah ,  Hon Wah Chew

IPC: H01L27/08 ,  H01L23/522 ,  H01L49/02

Abstract: An apparatus is provided which comprises: one or more dielectric layers forming a substrate, one or more first conductive contacts on a top surface of the substrate, one or more second conductive contacts on a bottom surface of the substrate opposite of the top surface, and one or more discrete capacitors conductively coupled with one or more of the first and second conductive contacts, the one or more discrete capacitors embedded within the substrate between the top surface and the bottom surface. Other embodiments are also disclosed and claimed.

公开(公告)号：US20160049316A1

公开(公告)日：2016-02-18

申请号：US14929046

申请日：2015-10-30

Applicant: Intel Corporation

Inventor： Tin Poay Chuah

IPC: H01L21/50 ,  H05K3/46 ,  H05K1/18 ,  H05K3/30

CPC classification number: H01L21/50 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/73267 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H05K1/185 ,  H05K3/30 ,  H05K3/4644 ,  H01L2924/00

Abstract: An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device.

Abstract translation: 一种包括印刷电路板的装置，包括导电材料和绝缘材料的多个交替层的主体; 以及包括设置在印刷电路板的主体内的管芯的封装。 一种包括形成印刷电路板的方法，所述印刷电路板包括芯和积层部分，所述堆积部分包括交替的导电材料层和耦合到所述芯的绝缘材料; 以及将包括管芯的封装耦合到所述印刷电路板的芯部，使得所述封装的侧壁的至少一部分嵌入所述堆积部分的至少一部分中。 一种包括本体的印刷电路板的设备; 包括包括布置在印刷电路板的主体内的微处理器的封装的计算设备; 以及向计算设备提供输入或输出的外围设备。

公开(公告)号：US20250113428A1

公开(公告)日：2025-04-03

申请号：US18478967

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Eng Huat Goh ,  Tin Poay Chuah ,  Kavitha Nagarajan ,  Telesphor Kamgaing ,  Poh Boon Khoo ,  Jiun Hann Sir

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34 ,  H05K3/40

Abstract: Technologies for a shield for electromagnetic interference include a circuit board with an integrated circuit package on it, with a hole in the circuit board under the integrated circuit package. The integrated circuit package may include one or more dies or other components on the underside of the package, at least partially positioned in the hole in the circuit board. An electromagnetic shield box can be positioned in the hole. Tabs of the electromagnetic shield box may interface with pads on the same side of the circuit board as the integrated circuit package. The electromagnetic shield box may prevent or reduce electromagnetic or radiofrequency interference on the components of the integrated circuit package. Positioning the electromagnetic shield box can reduce the overall height of the circuit board, among other advantages.