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公开(公告)号：US12250800B2
公开(公告)日：2025-03-11
申请号：US17482244
申请日：2021-09-22
Applicant: Intel Corporation
Inventor： Yew San Lim , Jeff Ku , Boon Ping Koh , Min Suet Lim , Tin Poay Chuah
Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a radiation shield that includes a zipper. The radiation shield can include a wall that extends from a support structure of the electronic device, a first portion that is coupled to a cold plate over a radiation source, a second portion that is coupled to the wall, and a zipper that can zip the first portion to the second portion together and can unzip to separate the first portion from the second portion.
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公开(公告)号：US11758662B2
公开(公告)日：2023-09-12
申请号：US17828142
申请日：2022-05-31
Applicant: Intel Corporation
Inventor： Tin Poay Chuah , Bok Eng Cheah , Jackson Chung Peng Kong
CPC classification number: H05K1/147 , H01R12/77 , H05K1/028 , H05K1/181 , H05K3/303 , H05K3/361 , H05K2201/055 , H05K2201/2018 , H05K2203/166
Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first rigid substrate, a second rigid substrate, a flexible substrate comprising a first portion attached to the first rigid substrate, a second portion attached to the second rigid substrate, a middle portion connecting the first portion to the second portion, wherein the middle portion is bent, and metallic traces therethrough, and a component forming a direct interface with the middle portion of the flexible substrate, the component electrically coupled to the metallic traces. In selected examples, the device further includes a casing.
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公开(公告)号：US11699664B2
公开(公告)日：2023-07-11
申请号：US17089756
申请日：2020-11-05
Applicant: Intel Corporation
Inventor： Eng Huat Goh , Tin Poay Chuah , Yew San Lim , Min Suet Lim
IPC: H01L23/552 , H05K3/28 , H05K1/02
CPC classification number: H01L23/552 , H05K1/0209 , H05K3/284
Abstract: According to the various aspects, the present device includes a printed circuit board having a top surface and a bottom surface, with a plurality of semiconductor devices coupled to the top surface and a flexible electromagnetic shield wrap conformally positioned over and between the plurality of semiconductor devices and the top surface of the printed circuit board. The flexible electromagnetic shield wrap is conformally positioned by applying a vacuum and is removable after the vacuum seal is broken.
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公开(公告)号：US20220369460A1
公开(公告)日：2022-11-17
申请号：US17828142
申请日：2022-05-31
Applicant: Intel Corporation
Inventor： Tin Poay Chuah , Bok Eng Cheah , Jackson Chung Peng Kong
Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first rigid substrate, a second rigid substrate, a flexible substrate comprising a first portion attached to the first rigid substrate, a second portion attached to the second rigid substrate, a middle portion connecting the first portion to the second portion, wherein the middle portion is bent, and metallic traces therethrough, and a component forming a direct interface with the middle portion of the flexible substrate, the component electrically coupled to the metallic traces. In selected examples, the device further includes a casing.
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公开(公告)号：US20220302006A1
公开(公告)日：2022-09-22
申请号：US17204587
申请日：2021-03-17
Applicant: Intel Corporation
Inventor： Santosh Gangal , Tin Poay Chuah
Abstract: Disclosed herein are via plug resistors for incorporation into electronic substrates, and related methods and devices. Exemplary via plug resistor structures include a resistive element within and on a surface of a via extending at least partially through an electronic substrate and first and second electrodes coupled to the resistive element.
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Patent Agency Ranking
公开(公告)号：US11375617B2
公开(公告)日：2022-06-28
申请号：US16887902
申请日：2020-05-29
Applicant: Intel Corporation
Inventor： Tin Poay Chuah , Bok Eng Cheah , Jackson Chung Peng Kong
Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first rigid substrate, a second rigid substrate, a flexible substrate comprising a first portion attached to the first rigid substrate, a second portion attached to the second rigid substrate, a middle portion connecting the first portion to the second portion, wherein the middle portion is bent, and metallic traces therethrough, and a component forming a direct interface with the middle portion of the flexible substrate, the component electrically coupled to the metallic traces. In selected examples, the device further includes a casing.
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公开(公告)号：US20220174820A1
公开(公告)日：2022-06-02
申请号：US17671566
申请日：2022-02-14
Applicant: Intel Corporation
Inventor： Mooi Ling Chang , Tin Poay Chuah , Eng Huat Goh , Min Suet Lim , Twan Sing Loo
Abstract: In one embodiment, a system includes a first circuit defining recesses along an edge of the first circuit board, and a second circuit board defining fins extending from at least one outer edge of the second circuit board. The fins of the second circuit board are positioned within the recesses of the second circuit board to connect the circuit boards in a co-planar manner. The fins and recesses may be shaped to provide an interlocking connection of the first and second circuit boards in the co-planar direction.
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公开(公告)号：US11343906B2
公开(公告)日：2022-05-24
申请号：US16988759
申请日：2020-08-10
Applicant: Intel Corporation
Inventor： Tai Loong Wong , Fern Nee Tan , Tin Poay Chuah , Min Suet Lim , Siang Yeong Tan
Abstract: The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.
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公开(公告)号：US10939540B2
公开(公告)日：2021-03-02
申请号：US16399825
申请日：2019-04-30
Applicant: Intel Corporation
Inventor： Tin Poay Chuah , Yew San Lim , Boon Ping Koh , Phaik Kiau Tan
Abstract: A folded circuit board includes a first circuit board and a second circuit board. The first circuit board and second circuit board are coupled together through a flexible interconnect. One or more folding guides are coupled to one of the first circuit board or second circuit board. The one or more folding guides extend beyond a first edge of the one of the first circuit board or second circuit board. The one or more folding guides include a curved sidewall configured to guide the flexible interconnect when the first circuit board is folded over the second circuit board. In one embodiment, the one or more folding guides are grounded to reduce EMI emissions.
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公开(公告)号：US10356902B2
公开(公告)日：2019-07-16
申请号：US14757984
申请日：2015-12-26
Applicant: INTEL CORPORATION
Inventor： Chee Ling Wong , Wil Choon Song , Khang Choong Yong , Eng Huat Goh , Mohd Muhaiyiddin Bin Abdullah , Tin Poay Chuah
Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.
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